Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric
AssigneeKilopass Technology, Inc.
InventorsJianguo Wang, David Fong, Jack Zezhong Peng, Fei Ye, Michael David Fliesler
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Abstract
A method of testing the programmability of a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises applying a test voltage across the data storage element. The select transistor is turned on. Finally, a current flow through the data storage element when the test voltage is applied is measured. A test positive signal is indicated if the current flow is greater than a reference.
Claims21
An apparatus for testing a memory cell, the memory cell comprising a select transistor and a data storage element, said select transistor having a gate connected to a select wordline, a source connected to a first terminal of said data storage element, and a drain connected to a column bitline, said apparatus comprising:
- a first column transistor connected to said column bitline;
- a wordline decoder connected to said gate of said select transistor through said select wordline, said wordline decoder providing an output signal to said select transistor to activate said select transistor, said wordline decoder also providing a test voltage to be applied to a second terminal of said data storage element;
- a sense amplifier that compares an input voltage to a reference voltage, said sense amplifier indicating that said memory cell tests programmable if said input voltage is higher than said reference voltage, said input voltage indicative of a Fowler-Nordheim current flowing through said data storage element.
An apparatus for testing a memory cell, the memory cell comprising a select transistor and a data storage element, said select transistor having a gate connected to a select wordline, a source connected to a first terminal of said data storage element, and a drain connected to a column bitline, said apparatus comprising:
- a first column transistor connected to said column bitline;
- a wordline decoder connected to said gate of said select transistor through said select wordline, said wordline decoder capable of turning on said select transistor, said wordline decoder also capable of providing a test voltage to a second terminal of said data storage element;
- means for measuring a current flowing through said data storage element when said test voltage is applied and providing a tests programmable signal if said current flow is greater than a reference.
A method of testing the programmability of a memory cell, the memory cell comprising a select transistor and a data storage element, said select transistor having a gate connected to a select wordline, a source connected to a first terminal of said data storage element, and a drain connected to a column bitline, said method comprising:
- applying a test voltage across said data storage element;
- turning on said select transistor;
- and
- measuring a current flow through said data storage element when said test voltage is applied and providing a test positive signal if said current flow is greater than a reference.
Dependencies are inferred from the claim text.