Semiconductor memory device
AssigneeOki Electric Industry Co., Ltd.
InventorsNorihiko Satani, Shinichiro Sato
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a redundant memory cell, an electrode and an output circuit. The redundant memory cell is used instead of a memory cell when the memory cell has a defect. The electrode applys with a test signal for setting a test condition from outside in testing the redundant memory cell. The output circuit outputs data read out of the memory cell and the redundant memory cell. When the test signal is applied to the electrode to set the test condition for the redundant memory cell, the output circuit is configured to output data read out of the redundant memory cell at a level different from a signal level of data readout of the memory cell for output.
Claims20
A semiconductor memory device comprising:
- a redundant memory cell for use instead of a memory cell when the memory cell has a defect;
- an electrode applied with a test signal for setting a test condition from outside in testing the redundant memory cell;
- and
- an output circuit for outputting data read out of the memory cell and the redundant memory cell,
- wherein when the test signal is applied to the electrode to set the test condition for the redundant memory cell, the output circuit is configured to output data read out of the redundant memory cell at a level different from a signal level of data read out of the memory cell for output.
A semiconductor memory device comprising:
- first and second redundant memory cells for use instead of a memory cell when the memory cell has a defect;
- first and second electrodes applied with a test signal for setting a test condition from outside in testing the first and second redundant memory cells;
- and
- an output circuit for outputting data read out of the memory cell and the first and second redundant memory cells,
- wherein when the test signal is applied to both the first and second electrodes to set the test condition for the first and second redundant memory cells, the output circuit is configured to output a signal at a fixed level.
A semiconductor memory device comprising:
- a redundant memory cell for use instead of a memory cell when the memory cell has a defect;
- an electrode applied with a test signal for setting a test condition from outside in testing the redundant memory cell;
- and
- an output circuit for outputting data read out of the memory cell and the redundant memory cell,
- wherein when the test signal is applied to the electrode to set the test condition for the redundant memory cell, the output circuit is configured to output data read out of the redundant memory cell at timing different from timing to output data read out of the memory cell.
Dependencies are inferred from the claim text.