US 7,031,204 B2 · Low power register apparatus having a two-way gating structure and method thereof

Abstract

A register apparatus and method for providing a two-way gating structure for receiving a write enable signal, a chip select signal, at least one read signal, and an address signal for a register. The apparatus and method comprise a two-way gating portion for generating a coded write address by AND-operating a first signal with the address signal, a coded read address by AND-operating a second signal with the address signal, and a reader activation signal by AND-operating the read signal with the second signal. The first and second signals are generated by AND-operating the chip select signal with the write enable signal and by AND-operating the chip select signal with an inverted write enable signal. A writer decodes the coded write address and generates write signals using the decoded write address and data received from a bus. A reader decodes the coded read address and generates data using data read from the register and the decoded read address.

Claims10

Dependent claims

A register apparatus having a two-way gating structure that receives a write enable signal, a chip select signal, at least one read signal, and an address signal for a register, comprising:

a two-way gating portion for generating a coded write address by AND-operating a first signal with the address signal, the first signal being generated by AND-operating the chip select signal with the write enable signal, generating a coded read address by AND-operating a second signal with the address signal, the second signal being generated by AND-operating the chip select signal with an inverted signal of the write enable signal, and generating a reader activation signal by AND-operating the at least one read signal with the second signal;
a writer for receiving the coded write address, decoding the coded write address, writing data using the decoded write address and the data received from a bus;
and
a reader for receiving the coded read address, decoding the coded read address, and outputting read signal to the bus using read signals and the decoded read address.

1 more element

A method for receiving a write enable signal, a chip select signal, at least one read signal, and an address signal for a register using a two-way gating structure, the method comprises:

generating via a two-way gating portion a coded write address by AND-operating a first signal with the address signal, the first signal being generated by AND-operating the chip select signal with the write enable signal, generating a coded read address by AND-operating a second signal with the address signal, the second signal being generated by AND-operating the chip select signal with an inverted signal of the write enable signal, and generating a reader activation signal by AND-operating the at least one read signal with the second signal;
receiving via a writer the coded write address, decoding the coded write address, writing data using the decoded write address and the data received from a bus;
and
receiving via a reader the coded read address, decoding the coded read address, and outputting read signal to the bus using read signals and the decoded read address.

1 more element

Dependencies are inferred from the claim text.

Low power register apparatus having a two-way gating structure and method thereof

Life of this patent

Low power register apparatus having a two-way gating structure and method thereof

Life of this patent

Abstract

Claims10