Floating-body DRAM using write word line for increased retention time

A method for controlling a memory cell having a transistor, comprising:

• controlling a gate voltage of the transistor with a first signal line;
• controlling a source voltage of the transistor with a second signal line;
• and
• inducing ionization current to flow from a drain area into a floating body of the transistor with a third signal line during a write operation, said ionization current causing the floating body to assume a potential corresponding to a first logical value.

A system, comprising:

• a circuit;
• and
• a memory cell array to store data for the circuit, said array including:
• (a) a first signal line to control a gate voltage of a cell transistor;
• (b) a second signal line to control a source voltage of the cell transistor;
• and
• (c) a third signal line to induce ionization current to flow from a drain area into a floating body of the cell transistor during a write operation, said ionization current causing the floating body to assume a potential corresponding to a logical data value, said logical data value controlled by said circuit.