Semiconductor memory device
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsNaoki Kuroda, Masashi Agata
Life of this patent
Estimating the term…
Abstract
A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.
Claims10
A semiconductor memory device, comprising:
- a first main amplifier activated in response to an active first enable signal, for amplifying data read from a first memory cell;
- a first tri-state buffer, configured to receive data provided by the first main amplifier, for driving an output node of the first tri-state buffer according to the data when the first enable signal is active and rendering the output node in a high impedance state when the first enable signal is inactive;
- and
- a first latch circuit for latching and outputting data of the output node of the first tri-state buffer to the outside.
A semiconductor memory device, comprising:
- an output buffer for outputting data read from a memory cell to an output terminal, wherein
- the output buffer includes
- a first buffer for receiving data read from the memory cell and driving the output terminal according to the data, and
- a second buffer, having an active state and an inactive state, for receiving the same data as the first buffer and driving the output terminal according to the data only in the active state, and
- the first buffer drives the output terminal irrespective of the active state and the inactive state.
A semiconductor memory device, comprising:
- an output buffer for outputting data read from a memory cell to an output terminal, wherein the output buffer includes
- a first buffer for driving the output terminal according to the data read from the memory cell, and
- a second buffer, having an active state and an inactive state, for driving the output terminal according to the read data in the active state;
- and
- the second buffer is activated and inactivated according to a bit width of the data read from the memory cell.
A semiconductor memory device, comprising:
- an output buffer for outputting data read from a memory cell to an output terminal;
- and
- a detector for detecting an operating frequency of the semiconductor memory device, wherein the output buffer includes
- a first buffer for driving the output terminal according to the data read from the memory cell, and
- a second buffer, having an active state and an inactive stated for driving the output terminal according to the read data in the active state;
- and
- the second buffer is activated and inactivated according to the operating frequency detected by the detector.
Dependencies are inferred from the claim text.