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US 7,031,192 B1Granted
Non-volatile semiconductor memory and driving method
AssigneeHalo LSI, Inc.
InventorsKi-Tae Park, Tomoko Ogura
Life of this patent
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Abstract
A data control unit is used to proved program, erase and verify signals to a non-volatile metal-oxide3-nitride-oxide-semiconductor (MONOS) memory. The data control unit comprises a plurality of sub-units that each contains a sense amplifier, two bi-directional flip-flop latches coupled in series and a program, erase and verify circuit. The two flip-flop latches each perform a task as a master latch or a slave latch depending on the memory operation. The program, erase and verify circuit in each sub-unit are connected together in a serial fashion such that multiple verification results are accumulated into one final result. Control signals are exchanged between a chip control unit and the data control unit to perform specified memory operations.
Claims27
A non-volatile semiconductor memory, comprising:
- a) an array of non-volatile MONOS (metal-oxide-nitride-oxide-semiconductor) memory cells,
- b) a control gate decoder coupled to control gates of said memory cells,
- c) a word line decoder coupled to word lines of said memory array,
- d) a bit line decoder coupled to bit lines of said memory array,
- e) a data control unit coupled to said bit line decoder,
- f) an input/output (I/O) interface unit coupled to a plurality of I/O data lines from the data control unit,
- g) a chip control unit controlling said control gate decoder, the word line decoder, the bit line decoder, the data control unit and the I/O interface unit,
- h) said data control unit containing a plurality of sub-units serially coupled together and coupling a verify signal, starting with a first sub-unit coupled to a second sub-unit and ending with said chip control unit coupled to a last sub-unit whereby a program and erase verify signal is coupled to said chip control unit indicating program and erase operations completed,
- i) each said sub-unit providing an inhibit voltage to the bit line coupled to said each sub-unit to prevent further current from flowing to said memory cell connected to the bit line upon completion of program and erase operation on said memory cell.
6 more elements
A data control unit, comprising:
- a) a means for a data control unit in a non-volatile MONOS (metal-oxide-nitride-oxide-semiconductor) memory,
- b) a means for a plurality of data control sub-units within said data control unit, each data control sub-unit containing a sense amplifier, a first flip-flop latch, a second flip-flop latch connected in series and further connected to a program, erase and verify circuit,
- c) a means for data to be coupled between said data control unit and a bit line decoder,
- d) a means for said data to be coupled between said data control unit and an input/output (I/O) interface unit,
- e) a means for control data to be sent and received between said data control unit and a chip control unit,
- f) a means for control of memory program, erase and verify operations,
- g) a means for inhibiting program and erase operations on an individual bit line when program and erase operations completed for said individual bit line.
4 more elements
A method to program a non-volatile memory array, comprising:
- a) selecting a page within a non-volatile MONOS (metal-oxide-nitride-oxide-semiconductor) memory using a control gate decoder controlled by a chip control unit,
- b) selecting a word line within said non-volatile MONOS memory using a word gate decoder controlled by said chip control unit,
- c) selecting said page within said non-volatile MONOS memory using a bit line decoder controlled by said chip control unit,
- d) receiving data into a first and a second data control sub-unit from an input/output interface unit, where each data control sub-unit comprises a two stage latch wherein a first stage of said two stage latch is a master flip-flop latch and second stage of said two stage latch is a slave flip-flop latch,
- e) transferring said data from said master flip-flop latch to said slave flip-flop latch within each said data control sub-unit,
- f) producing a program voltage in accordance with said data to perform a program operation on a first memory cell connected to said first data control sub-unit and a second memory cell connected to said second data control sub-unit,
- g) coupling said program voltage to said first and said second memory cells selected by the control gate decoder, the word line decoder and the bit line decoder,
- h) creating a first program verify signal in said first data control sub-unit and a second program verify signal in said second data control sub-unit,
- i) coupling said first program verify signal to said second data control sub-unit when said first memory cell is programmed,
- j) combining said first program verify signal with said second program verify signal in said second data control sub-unit and coupling a combined said first and second verify signal to a third data control sub-unit until a last data sub-unit couples a final verify signal to said chip control unit.
7 more elements
A method to read a non-volatile memory array, comprising:
- a) selecting a page within a non-volatile MONOS (metal-oxide-nitride-oxide-semiconductor) memory using a control gate decoder,
- b) selecting a word line within said non-volatile MONOS memory using a word gate decoder,
- c) selecting said page within said non-volatile MONOS memory using a bit line decoder,
- d) receiving data into a sense amplifier from a bit line of a selected cell,
- e) coupling said data from output of said sense amplifier to a two stage latch wherein a first stage of said two stage latch is a master flip-flop latch and a second stage of said two stage latch is a slave flip-flop latch,
- f) transferring said data from said master flip-flop latch to said slave flip-flop latch,
- g) coupling said data from said slave flip-flop latch to said data output/input (I/O).
4 more elements
Dependencies are inferred from the claim text.