Stabilization method for drain voltage in non-volatile multi-level memory cells and related memory device
AssigneeSTMicroelectronics S.r.l.
InventorsLuca Crippa, Giancarlo Ragone
Life of this patent
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Abstract
A method and an electronic device for stabilizing the voltage on the drain terminals of multi-level non-volatile memory cells during programming thereof. The voltage is provided by a drain voltage regulator having an output connected to the drain terminals at a common circuit node by a metal line conduction path having a parasitic intrinsic resistance. A feedback path is advantageously provided between the common circuit node and an input of the regulator.
Claims19
A method for programming an electronic memory device comprising a plurality of non-volatile memory cells each having a conduction terminal associated therewith, a voltage regulator having at least one input and an output, and a conductor having a first end connected to the output of the voltage regulator and a second end connected to a common circuit node also connected to each of the conduction terminals, the method comprising:
- outputting a first voltage from the output of the voltage regulator to the first end of the conductor, the conductor having a parasitic intrinsic resistance associated therewith;
- and
- feeding back a second voltage from the common circuit node along a feedback path to the at least one input of the voltage regulator.
A method for supplying power to a load from among a plurality of loads each connected to a conductor having first and second ends, the method comprising:
- applying a first voltage to the first end of the conductor using a voltage regulator, the voltage regulator having at least one input and an output and being connected to the first end of the conductor at the output, and the conductor having at least one routing resistance associated therewith;
- and
- feeding back a second voltage from the second end of the conductor along a feedback path to the at least one input of the voltage regulator.
An electronic memory device comprising:
- a programming circuit having at least one input and an output;
- a plurality of non-volatile memory cells each having a conduction terminal associated therewith;
- a conductor having a first end connected to the output of said programming circuit and a second end connected to a common circuit node, the common circuit node also being connected to each of the conduction terminals, the conductor having a parasitic intrinsic resistance associated therewith;
- and
- a feedback path connected between the common circuit node and the at least one input of said programming circuit.
Dependencies are inferred from the claim text.