Structure for testing NAND flash memory and method of testing NAND flash memory

A structure for testing a NAND flash memory, comprising:

• a first string select transistor for controlling transfer of a voltage inputted via a first bit line;
• a first string having a plurality of flash memory cells, connected between the first string select transistor and a first source select transistor, and maintaining a program state or an erase state depending on a voltage inputted thereto;
• a second string select transistor for controlling transfer of a voltage inputted via a second bit line;
• a second string having a plurality of flash memory cells, connected between the second string select transistor and a second source select transistor, and maintaining the program state or the erase state depending on a voltage inputted thereto;
• and
• a measurement pad connected to a point where the first or the second source select transistor and an adjacent flash memory cell are connected.

A method of testing a NAND flash memory, comprising the steps of:

• providing structure for testing the NAND flash memory, the structure comprising:
• a first string select transistor for controlling transfer of a voltage inputted via a first bit line;
• a first string having a plurality of flash memory cells, connected between the first string select transistor and a first source select transistor, and maintaining a program state or an erase state depending on a voltage inputted thereto;
• a second string select transistor for controlling transfer of a voltage inputted via a second bit line;
• a second string having a plurality of flash memory cells, connected between the second string select transistor and a second source select transistor, and maintaining the program state or the erase state depending on a voltage inputted thereto;
• and
• a measurement pad connected to a point where the first or the second string select transistor and an adjacent flash memory cell are connected;
• selecting the first or the second string, wherein a voltage of 0V is applied to a selected string and Vcc is applied to a non-selected string, while applying a program voltage to control gates of all the flash memory cells in a column to be programmed in the selected string, a pass voltage to control gates of remaining flash memory cells, a first gate voltage to a gate of the string select transistor, and a voltage of 0V to the source select transistor;
• and
• measuring a voltage between the measurement pad and a common source line.

A method of testing a NAND flash memory, comprising the steps of:

• providing structure for testing the NAND flash memory, the structure comprising:
• a first string select transistor for controlling transfer of a voltage inputted via a first bit line:
• a first string having a plurality of flash memory cells, connected between the first string select transistor and a first source select transistor, and maintaining a program state or an erase state depending on a voltage inputted thereto;
• a second string select transistor for controlling transfer of a voltage inputted via a second bit line;
• a second string having a plurality of flash memory cells, connected between the second string select transistor and a second source select transistor, and maintaining the program state or the erase state depending on a voltage inputted thereto;
• and
• a measurement pad connected to a point where the first or the second source select transistor and an adjacent flash memory cell are connected;
• selecting the first or second string, wherein a voltage of 0V is applied to a selected string and Vcc is applied to a non-selected string, while applying a program voltage to control gates of all the flash memory cells in a column to be programmed in the selected string, a pass voltage to control gates of remaining flash memory cells, a first gate voltage to a gate of the string select transistor, and a voltage of 0V to the source select transistor;
• and
• measuring a voltage between the measurement pad and a common source line.

A structure for testing a NAND flash memory, comprising:

• a first string select transistor for controlling transfer of a voltage inputted via a first bit line;
• a first string having a plurality of flash memory cells, connected between the first string select transistor and a first source select transistor, and maintaining a program state or an erase state depending on a voltage inputted thereto;
• a second string select transistor for controlling transfer of a voltage inputted via a second bit line;
• a second string having a plurality of flash memory cells, connected between the second string select transistor and a second source select transistor, and maintaining the program state or the erase state depending on a voltage inputted thereto;
• a first switching device connected between a point where the first string select transistor and a flash memory cell adjacent to the first string select transistor are connected and a first measurement pad;
• and
• a second switching device connected between a point where the second string select transistor and a flash memory cell adjacent to the second string select transistor are connected and a second measurement pad.

A structure for testing a NAND flash memory, comprising:

• a first string select transistor for controlling transfer of a voltage inputted via a first bit line;
• a first string having a plurality of flash memory cells, connected between the first string select transistor and a first source select transistor, and maintaining a program state or an erase state depending on a voltage inputted thereto;
• a second string select transistor for controlling transfer of a voltage inputted via a second bit line;
• a second string having a plurality of flash memory cells, connected between the second string select transistor and a second source select transistor, and maintaining the program state or the erase state depending on a voltage inputted thereto;
• a first switching device connected between a point where the first source select transistor and a flash memory cell adjacent to the first source select transistor are connected and a first measurement pad;
• and
• a second switching device connected between a point where the second source select transistor and a flash memory cell adjacent to the second source select transistor are connected and a second measurement pad.

A method of testing a NAND flash memory, comprising the steps of:

• providing structure for testing the NAND flash memory, the structure comprising:
• a first string select transistor for controlling transfer of a voltage inputted via a first bit line;
• a first string having a plurality of flash memory cells, connected between the first string select transistor and a first source select transistor, and maintaining a program state or an erase state depending on a voltage inputted thereto;
• a second string select transistor for controlling transfer of a voltage inputted via a second bit line;
• a second string having a plurality of flash memory cells, connected between the second string select transistor and a second source select transistor, and maintaining the program state or the erase state depending on a voltage inputted thereto,
• a first switching device connected between a point where the first string select transistor and a flash memory cell adjacent to the first string select transistor are connected and a first measurement pad;
• and
• a second switching device connected between a point where the second string select transistor and a flash memory cell adjacent to the second string select transistor are connected and a second measurement pad;
• selecting the first or the second string, wherein a voltage of 0V is applied to a selected string and Vcc is applied to a non-selected string, while applying a program voltage to control gates of all the flash memory cells in a column to be programmed in the selected string, a pass voltage to control gates of remaining flash memory cells, a first gate voltage to a gate of the string select transistor, and a voltage of 0V to the source select transistor;
• turning on the switching device connected to the selected string;
• and
• measuring a voltage between the measurement pad and a source line.

A method of testing a NAND flash memory, comprising the steps of:

• providing structure for testing the NAND flash memory, the structure comprising:
• a first string select transistor for controlling transfer of a voltage inputted via a first bit line;
• a first string having a plurality of flash memory cells, connected between the first string select transistor and a first source select transistor, and maintaining a program state or an erase state depending on a voltage inputted thereto;
• a second string select transistor for controlling transfer of a voltage inputted via a second bit line;
• a second string having a plurality of flash memory cells, connected between the second string select transistor and a second source select transistor, and maintaining the program state or the erase state depending on a voltage inputted thereto;
• a first switching device connected between a point where the first source select transistor and a flash memory cell adjacent to the first source select transistor are connected and a first measurement pad;
• and
• a second switching device connected between a point where the second source select transistor and a flash memory cell adjacent to the second source select transistor are connected and a second measurement pad;
• selecting the first or second string, wherein a voltage of 0V is applied to a selected string and Vcc is applied to a non-selected string, while applying a program voltage to control gates of all the flash memory cells in a column to be programmed in the selected string, a pass voltage to control gates of remaining flash memory cells, a first gate voltage to a gate of the string select transistor, and a voltage of 0V to the source select transistor;
• turning on the switching device connected to the selected string;
• and
• measuring a voltage between the measurement pad and a source line.