Memory system having flash memory where a one-time programmable block is included

A memory system, comprising:

• a flash memory device including a one-time programmable block where protection data information is stored in a predetermined region;
• and
• an interface device including a register to store one-time programmable lock status information that indicates whether the one-time programmable block is programmed, wherein the flash memory device comprises:
• a memory block;
• a memory block selection circuit for selecting the memory block;
• a one-time programmable block selection circuit for selecting the one-time programmable block;
• and
• a control circuit for setting the memory block selection circuit to an inactive state and the one-time programmable block selection circuit to an active state, respectively, so as to cut off an access to the memory block in a one-time programmable mode.

A memory system, comprising:

• a flash memory device including a one-time programmable block where the protection data information is stored in a predetermined region;
• and
• an interface device including a register to store one-time programmable lock status information that indicates whether the one-time programmable block is programmed, wherein the flash memory device further comprises:
• a memory block;
• a memory block selection circuit for selecting the memory block;
• a one-time programmable block selection circuit for selecting the one-time programmable block;
• an address buffer circuit to output block addresses and row addresses applied from the interface device to the memory block selection circuit and the one-time programmable block selection circuit;
• and
• a control circuit to generate a one-time programmable enable signal in response to a command to notify of a one-time programmable mode, wherein the memory block is not selected by the memory block selection circuit regardless of the block addresses when the one-time programmable enable signal is activated, and the one-time programmable block selection circuit selects the one-time programmable block in response to an activated one-time programmable enable signal.

A memory system comprising:

• a flash memory device including a one-time programmable block where test information is stored;
• a power-on reset read enable signal generator circuit to generate a power-on reset read enable signal at power-up;
• and
• an interface device control an access to the flash memory device in response to the power-on reset read enable signal so that the test information in the one-time programmable block is accessed without an external command at power-up.