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US 7,031,181 B1Granted
Multi-pulse reset write scheme for phase-change memories
AssigneeInfineon Technologies AG
InventorThomas Happ
Life of this patent
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Abstract
A memory cell device and method that includes a memory cell, and first and second write pulse signals. The memory cell has phase-change material capable of being set and capable of being reset. The first and second write pulse signals are used for a single reset operation of the memory cell. The first write pulse signal heats and melts a first portion of the phase-change material of the memory cell. The second write pulse signal heats and melts a second portion of the phase-change material of the memory cell.
Claims20
A method of resetting a memory cell, the method comprising:
- providing a first electrical write pulse to phase-change material within the memory cell;
- heating a first portion of the phase-change material with the first write pulse until it is melted;
- allowing the first portion of the phase-change material to cool below melting temperate;
- providing a second write pulse to the phase-change material within the memory cell;
- heating a second portion of the phase-change material with the second write pulse until it is melted;
- and
- allowing the second portion of the phase-change material to cool.
4 more elements
A memory cell device comprising:
- a memory cell having phase-change material capable of being set and capable of being reset;
- write pulse means for generating at least first and second write pulse signals for a single reset operation of the memory cell, wherein the first write pulse signal heats and melts a first portion of the phase-change material of the memory cell, and wherein the second write pulse signal heats and melts a second portion of the phase-change material of the memory cell.
A memory device comprising:
- a plurality of phase-change memory cells each having phase-change material that can be set and reset;
- a write pulse generator that generates at least first and second write pulse signals for a single reset operation;
- and
- a distribution circuit for distributing the first and second write pulse signals for a single reset operation to a selected memory cell;
- wherein the first write pulse signal heats and melts a first portion of the phase-change material of the selected memory cell, and wherein the second write pulse signal heats and melts a second portion of the phase-change material of the selected memory cell.
2 more elements
Dependencies are inferred from the claim text.