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US 7,031,177 B2Granted
Non-volatile and-type content addressable memory
AssigneeSTMicroelectronics S.r.l.
InventorGuido de Sandre
Life of this patent
Estimating the term…
Abstract
In order to speed up the search for a data item in the memory and simplify the circuit structure of the memory, with each row of cells there is associated a ground control line, a ground line and a match control line. Furthermore, with every row of cells there is associated a search activation terminal and a match indication terminal.
Claims14
A non-volatile content addressable memory, comprising:
- a multiplicity of memory cells ordered into a matrix of rows and columns;
- a word line associated with every row of cells;
- a first and a second bit line associated with every column of cells;
- an input terminal and an output terminal;
- a ground control line, a ground line and a match control line associated with every row of cells;
- a search activation terminal and a match indication terminal associated with every row of cells;
- each cell comprising:
- a first non-volatile memory element having a control terminal connected to the word line associated with the row containing the cell, a first terminal connected to the first bit line associated with the column containing the cell and a second terminal connected to a match node of the cell;
- a second non-volatile memory element having a control terminal connected to the word line associated with the row containing the cell, a first terminal connected to the second bit line associated with the column containing the cell and a second terminal connected to the match node of the cell;
- a first controlled electronic switch connected between the input terminal and the output terminal of the cell and having a control terminal connected to the match node of the cell, the controlled electronic switches of the cells of the same row being connected in series with each other between the search activation terminal and the match indication terminal associated with the row;
- a second controlled electronic switch connected between the ground line associated with the row containing the cell and the cell output terminal and having a control terminal connected to the match control line associated with the row containing the cell;
- and
- a third controlled electronic switch connected between the match node of the cell and the ground line associated with the row containing the cell and having a control terminal connected to the ground control line associated with the row containing the cell.
10 more elements
A content addressable memory, comprising:
- a plurality of memory cells arranged in a matrix of rows and columns and having a word line associated with every row and first and second bit lines associated with every column;
- an input terminal and an output terminal;
- a ground control line, a ground line, a match control line, a search activation terminal, and a match indication terminal associated with every row of cells;
- the matrix of memory cells configured to generate a match signal whenever a voltage on the match indication terminal varies, and generating a no-match signal when a voltage on the match indication terminal does not vary.
1 more element
A memory cell for a content addressable memory, the cell comprising:
- a first non-volatile memory element having a control terminal connected to word line associated with the cell, a first terminal connected to a first bit line associated with the cell, and a second terminal connected to a match node of the cell;
- a second non-volatile memory element having a control terminal connected to the word line, a first terminal connected to a second bit line associated with the cell, and a second terminal connected to the match node of the cell;
- a first controlled electronic switch connected between an input terminal associated with the memory cell and an output terminal associated with the memory cell, the first controlled electronic switch having a control terminal connected to the match node, the first controlled electronic switch configured to be coupled in series in a row of memory cells between a search activation terminal and a match indication terminal associated with the row;
- a second controlled electronic switch connected between a ground line associated with the cell and the output terminal, and further having a control terminal configured for connection to a match control line associated with the row in which the cell is coupled;
- and
- a third controlled electronic switch coupled between the match node and the ground line, and further having a control terminal configured for connection to a ground control line associated with the row in which the cell is configured to be coupled.
3 more elements
A memory, comprising:
- a plurality of memory cells arranged in rows and columns forming a memory matrix, each memory cell comprising:
- a first transistor having a control gate coupled to a word line, a first terminal coupled to a first bit line, and a second terminal coupled to a first node;
- a second transistor having a control gate coupled to the word line, a first terminal coupled to a second bit line, and a third terminal coupled to the first node;
- a third transistor having a control gate coupled to a control line, a first terminal coupled to the first node, and a second terminal coupled to a voltage reference source;
- a fourth transistor having a control gate coupled to a match control line, a first terminal coupled to the voltage reference source, and a second terminal coupled to a match output line;
- and
- a fifth transistor having a control gate coupled to the first node, a first terminal coupled to the match output line, and a second terminal coupled to a match input line.
4 more elements
A computer system, comprising:
- a microprocessor having a memory associated therewith, the memory comprising:
- a plurality of memory cells arranged in rows and columns forming a memory matrix, each memory cell comprising:
- a first transistor having a control gate coupled to a word line, a first terminal coupled to a first bit line, and a second terminal coupled to a first node;
- a second transistor having a control gate coupled to the word line, a first terminal coupled to a second bit line, and a third terminal coupled to the first node;
- a third transistor having a control gate coupled to a control line, a first terminal coupled to the first node, and a second terminal coupled to a voltage reference source;
- a fourth transistor having a control gate coupled to a match control line, a first terminal coupled to the voltage reference source, and a second terminal coupled to a match output line;
- and
- a fifth transistor having a control gate coupled to the first node, a first terminal coupled to the match output line, and a second terminal coupled to a match input line.
5 more elements
Dependencies are inferred from the claim text.