US 7,031,175 B2 · System and method of detecting phase body diode using a comparator in a synchronous rectified FET driver

Abstract

A body diode comparator circuit for a synchronous rectified FET driver including a sample circuit and a comparator. The FET driver has a phase node coupled between a pair of upper and lower switching FETs and is responsive to a PWM signal having first and second phases for each cycle. The sample circuit samples an initial voltage of the phase node during the first phase of the PWM signal and provides a sum voltage indicative of the initial phase voltage added to the voltage level of the phase node during the second phase of the PWM signal. The comparator compares the sum voltage with a predetermined reference voltage and provides an output indicative of an activation state of the lower FET during the second phase of the PWM signal. The FET driver turns on the upper FET when the comparator indicates that the lower FET is off.

Claims20

Dependent claims

A body diode comparator circuit for a synchronous rectified FET driver, wherein the driver is responsive to a PWM signal and has a phase node coupled between upper and lower switching FETs, and wherein the PWM signal has first and second phases for each PWM cycle, said body diode comparator circuit comprising:

a sample circuit for sampling an initial voltage of the phase node during the first phase of the PWM signal and for providing a sum voltage indicative of said initial voltage added to the voltage level of the phase node during the second phase of the PWM signal;
and
a comparator that compares said sum voltage with a predetermined reference voltage and that provides an output indicative of an activation state of the lower FET during the second phase of the PWM signal.

A rectified synchronous FET power regulator, comprising:

an upper FET and a lower FET coupled together at a phase node and coupled between an input voltage signal and a reference terminal of a voltage source;
PWM logic that switches said upper and lower FETs based on a PWM signal having first and second states;
and
a comparator circuit, coupled to said phase node and said PWM logic, that detects activation state of said lower FET, said comparator circuit comprising:
a sample circuit that samples an initial voltage of said phase node during said first state of said PWM signal and that provides a sum voltage indicative of a sum of said initial voltage and the voltage level of said phase node during said second state of said PWM signal;
and
a comparator that compares said sum voltage with a predetermined reference voltage and that provides an output indicative of said activation state of said lower FET.

4 more elements

Dependencies are inferred from the claim text.

System and method of detecting phase body diode using a comparator in a synchronous rectified FET driver

Life of this patent

System and method of detecting phase body diode using a comparator in a synchronous rectified FET driver

Life of this patent

Abstract

Claims20