Analog-to-digital converter and method of analog-to-digital conversion

A method of converting an analog voltage signal into a digital signal by use of first and second pulse-phase-difference coding circuits each of which includes:

• a pulse-circulating circuit having a plurality of delay gates connected in a form of a ring, delay times of said delay gates depending on a voltage applied to said delay gates as a power supply voltage thereof;
• a counter outputting a count signal representing the number of times that a pulse circulating in said pulse-circulating circuit has traveled around said pulse-circulating circuit during a sampling time defined by a phase difference between sampling control signals supplied to said pulse-circulating circuit,
• a position signal generating device generating a position signal representing a position of said pulse within said pulse-circulating circuit;
• and
• a processing circuit outputting a combination of said count signal and said position signal as an A/D-converted data set of said voltage applied to said delay gates;
• said method comprising the steps of:
• supplying said first pulse-phase-difference coding circuit with a reference voltage as said power supply voltage during a first time period and with an analog voltage signal outputted from an amplifier as said power supply voltage during a second time period, while supplying said second pulse-phase-difference coding circuit with said reference voltage as said power supply voltage during said first and second time periods, said amplifier using said reference voltage as a potential base thereof;
• supplying said first and second pulse-phase-difference coding circuits with said sampling control signals during each of said first and second time periods,
• storing, in a register, a first data set outputted from said processing circuit of said first pulse-phase-difference coding circuit as an A/D-converted data set of said reference voltage when said pulse-phase-difference coding circuit is supplied with said reference voltage as said power supply voltage during said first time period;
• correcting a second data set outputted from said processing circuit of said first pulse-phase-difference coding circuit as an A/D-converted data set of said analog voltage signal when said first pulse-phase-difference coding circuit is supplied with said analog voltage signal as said power supply voltage on the basis of difference between one of said first data set and a third data set outputted from said processing circuit of said second pulse-phase-difference coding circuit as an A/D-converted data set of said reference voltage when said first pulse-phase-difference coding circuit is supplied with said reference voltage as said power supply voltage, and a fourth data set outputted from said processing circuit of said second pulse-phase-difference coding circuit as an A/D-converted data set of said reference voltage when said first pulse-phase-difference coding circuit is supplied with said analog voltage signal as said power supply voltage;
• and
• dividing said second data set corrected by said first data set stored in said register.

An A/D converter for converting an analog voltage signal into a digital signal comprising:

• first and second pulse-phase-difference coding circuits each of which includes:
• a pulse-circulating circuit having a plurality of delay gates connected in a form of a ring, delay times of said delay gates depending on a voltage applied to said delay gates as a power supply voltage thereof;
• a counter outputting a count signal representing the number of times that a pulse circulating in said pulse-circulating circuit has traveled around said pulse-circulating circuit during a sampling time defined by a phase difference between sampling control signals supplied to said pulse-circulating circuit,
• a position signal generating device generating a position signal representing a position of said pulse within said pulse-circulating circuit;
• and
• a processing circuit outputting a combination of said count signal and said position signal as an A/D-converted data set of said voltage applied to said delay gates;
• an input selection switch which selects, in response to a selection signal, one of a reference voltage, a high compensation voltage higher than said reference voltage, a low compensation voltage lower than said reference voltage, and said analog voltage signal which is supplied from an amplifier, said amplifier amplifying said analog voltage signal using said reference voltage as a base potential thereof;
• a control circuit operating to supply said input selection switch with said selection signal so that said first pulse-phase-difference coding circuit is supplied, as said power supply voltage, with said reference voltage, said high compensation voltage, said low compensation voltage, and said analog voltage signal in an alternating sequence, to supply said second pulse-phase-difference coding circuit with said reference voltage as said power supply voltage continuously, and to supply said pulse-circulating circuits of said first and second pulse-phase-difference coding circuits with said sampling control signals so that said first pulse-phase-difference coding circuit outputs A/D-converted data sets of said reference voltage, said high compensation voltage, said low compensation voltage and said analog voltage signal in an alternating sequence, and that said second pulse-phase-difference coding circuit outputs a first A/D-converted data set of said reference voltage when said first pulse-phase-difference coding circuit is supplied with said reference voltage, and a second A/D-converted data set of said reference voltage when said first pulse-phase-difference coding circuit is supplied with said analog voltage signal,
• a variation compensation circuit correcting said A/D-converted data set of said analog voltage signal outputted from said first pulse-phase-difference coding circuit on the basis of difference between said first and second A/D-converted data sets outputted from said second pulse-phase-difference coding circuit;
• and
• a nonlinearity compensation device that determines three compensation factors from said A/D-converted data sets of said reference voltage, said high compensation voltage and said low compensation voltage outputted from said first pulse-phase-difference coding circuit, and corrects said A/D-converted data set of said analog voltage signal by performing a second-order compensation using said three compensation factors to compensate for non linearity of said first pulse-phase-difference coding circuit.

A method of converting an analog voltage signal into a digital signal by use of first and second pulse-phase-difference coding circuits each of which includes:

• a pulse-circulating circuit having a plurality of delay gates connected in a from of a ring, delay times of said delay gates depending on a voltage applied to said delay gates as a power supply voltage thereof;
• a counter outputting a count signal representing the number of times that a pulse circulating in said pulse-circulating circuit has traveled around said pulse-circulating circuit during a sampling time defined by a phase difference between sampling control signals supplied to said pulse-circulating circuit,
• a position signal generating device generating a position signal representing a position of said pulse within said pulse-circulating circuit;
• and
• a processing circuit outputting a combination of said count signal and said position signal as an A/D-converted data set of said voltage applied to said delay gates;
• said method comprising the steps of:
• supplying, as said power supply voltage, said first pulse-phase-difference coding circuit with, in an alternating sequence, a reference voltage, a high compensation voltage higher than said reference voltage, a low compensation voltage lower than said reference voltage and said analog voltage signal which is supplied from an amplifier, said amplifier amplifying said analog voltage signal using said reference voltage as a base potential thereof, while supplying said second pulse-phase-difference coding circuit with said reference voltage as said power supply voltage continuously;
• supplying said pulse-circulating circuits of said first and second pulse-phase-difference coding circuits with said sampling control signals so that said first pulse-phase-difference coding circuit outputs A/D-converted data sets of said reference voltage, said high compensation voltage, said low compensation voltage and said analog voltage signal in an alternating sequence, and said second pulse-phase-difference coding circuit outputs a first A/D-converted data set of said reference voltage when said first pulse-phase-difference coding circuit is supplied with said reference voltage, and a second A/D-converted data set of said reference voltage when said first pulse-phase-difference coding circuit is supplied with said analog voltage signal,
• correcting said A/D-converted data set of said analog voltage signal outputted from said first pulse-phase-difference coding circuit on the basis of difference between said first and second A/D-converted data sets outputted from said second pulse-phase-difference coding circuit;
• determining three compensation factors from said A/D-converted data sets of said reference voltage, said high compensation voltage and said low compensation voltage outputted from said first pulse-phase-difference coding circuit;
• and correcting said A/D-converted data set of said analog voltage signal by performing a second-order compensation using said three compensation factors to compensate for nonlinearity of said first pulse-phase-difference coding circuit.

An A/D converter for converting an analog voltage signal into a digital signal comprising:

• a pulse-phase-difference coding circuit which includes:
• a pulse-circulating circuit having a plurality of delay gates connected in a form of a ring, delay times of said delay gates depending on a voltage applied to said delay gates as a power supply voltage thereof;
• a counter outputting a count signal representing the number of times that a pulse circulating in said pulse-circulating circuit has traveled around said pulse-circulating circuit during a sampling time defined by a phase difference between sampling control signals supplied to said pulse-circulating circuit;
• and
• a position signal generating device generating a position signal representing a position of said pulse within said pulse-circulating circuit;
• said pulse-phase-difference coding circuit outputting a combination of said count signal and said position signal as an A/D-converted data of an analog voltage signal applied to said delay gates as said power supply voltage;
• a control circuit operating to supply said pulse-circulating circuit with said sampling control signals in order that said counter outputs said count signal and said position signal generating device generates said position signal at each lapse of said sampling time;
• a differential data set calculating device outputting a differential data set representing a difference between two A/D-converted data sets of said analog voltage signal successively outputted from said pulse-phase-difference coding circuit;
• and
• a digital low-pass filter filtering said differential data set outputted from said differential data set calculating device.

A method of converting an analog voltage signal into a digital signal by use of a pulse-phase-difference coding circuit which includes:

• a pulse-circulating circuit having a plurality of delay gates connected in a form of a ring, delay times of said delay gates depending on a voltage applied to said delay gates as a power supply voltage thereof;
• a counter outputting a count signal representing the number of times that a pulse circulating in said pulse-circulating circuit has traveled around said pulse-circulating circuit during a sampling time defined by a phase difference between sampling control signals supplied to said pulse-circulating circuit;
• and
• a position signal generating device generating a position signal representing a position of said pulse within said pulse-circulating circuit;
• said pulse-phase-difference coding circuit outputting a combination of said count signal and said position signal as A/D-converted data of an analog voltage signal applied to said delay gates as said power supply voltage;
• said method comprising the steps of:
• supplying said pulse-circulating circuit with said sampling control signals in order that said counter outputs said count signal and said position data generating device generates said position signal at each lapse of said sampling time;
• calculating a differential data set representing a difference between two A/D-converted data sets of said analog voltage signal successively outputted from said pulse-phase-difference coding circuit;
• and
• low-pass filtering said differential data set.