Suppressing digital-to-analog converter (DAC) error
AssigneeTexas Instruments Incorporated
InventorFeng Chen
Life of this patent
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Abstract
A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that is part of a modulator (FIG. 6). A low pass averaging (LPA) index decoder 650 controls a shifting arrangement 635 to shift a digital word T2 derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. 5). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder 650 causes the shifting arrangement 635 to shift the digital word T2 using only a single pointer per clock cycle.
Claims8
A shifting arrangement, comprising:
- a shifter configured to shift a digital input word in a first direction on even-numbered clock cycles and in a second direction opposite the first direction on odd-numbered clock cycles that alternate with the even-numbered clock cycles, and to provide a resulting shifted digital word that constitutes the digital input word shifted by a number of bit positions determined by a shift control word;
- and
- a decoder, configured to calculate, based at least in part on the shifted digital word, the shift control word that determines a number of bits by which the shifter shifts the digital input word to form the resulting shifted digital word.
Dependencies are inferred from the claim text.