Circuit and method for use in data compression

A compression arrangement for performing data compression of a data string, said compression arrangement comprising:

• an input buffer for holding a first sequence of bytes of said data string;
• a history buffer for holding a second sequence of bytes of said data string;
• a comparison matrix coupled to said input buffer and said history buffer, wherein each column of said comparison matrix is formed by a plurality of “triangle” logic gate stages connected in series, wherein each of said plurality of “triangle” logic gate stages is arranged to produce a carry value for passing to another one of said plurality of “triangle” logic gate stages, wherein the product of the number stages in said plurality of “triangle” logic gate stages and the number logic gates in each of said plurality of “triangle” logic gate stages is less than the number of logic gates required for an equivalent circuit having a single logic circuit stage;
• an input latch coupled to an input of said comparison matrix for receiving a carry value from another carry-value-producing circuit;
• means for producing a look-ahead carry value coupled to a predetermined number of said plurality of “triangle” logic gate stages for producing a look-ahead carry value;
• a MAX function/priority encoder for detecting a row of said comparison units and preceding comparison units in the same column in which a largest number of consecutive byte matches occurred;
• and
• a token encoder for encoding as a token a sequence of matched bytes detected by said MAX function/priority encoder.