Level shifter that provides high-speed operation between power domains that have a large voltage difference
AssigneeNational Semiconductor Corporation
InventorsAlexander Burinskiy, Vladislav Potanin, Elena Potanina
Life of this patent
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Abstract
The speed of a level shifter, which translates a first voltage in a first power domain to a second voltage in a second power domain, is increased by utilizing a first bipolar transistor to assist a first MOS transistor in pulling down the voltage on a first output node, and a second bipolar transistor to assist a second MOS transistor in pulling down the voltage on a second output node.
Claims19
A level shifter comprising:
- an inverter having an input node and an intermediate node, the input node having a logic state, the intermediate node having a logic state opposite of the logic state of the input node;
- a first transistor that contacts the inverter and a first output node, the first output node having a logic state;
- a second transistor that contacts the inverter and a second output node, the second output node having a logic state opposite the logic state of the first output node;
- a third transistor that contacts the first transistor and the first output node;
- a fourth transistor that contacts the second transistor and the second output node;
- a fifth transistor that contacts the second transistor;
- a sixth transistor that contacts the fifth transistor;
- and
- a seventh transistor that contacts the fifth transistor, the sixth transistor, and the second output node.
A method of level shifting a voltage, the method comprising pulling down an intermediate voltage on a first intermediate node to a first value when an input voltage on an input node has a logic high, the first value turning off a first transistor and a second transistor, the logic high turning on a third transistor and a fourth transistor, the third transistor pulling down an output voltage on an inverting output node, the fourth transistor pulling down an intermediate voltage on a second intermediate node to a second value, the second value turning on a fifth transistor that pulls down the output voltage on the inverting output node.
A level shifter comprising:
- a level shifting circuit having an input, an inverted output, and a non-inverted output, a logic high at the input having a first voltage, a logic high at the inverted output having a second voltage, a logic high at the non-inverted output having the second voltage, the second voltage being greater than the first voltage;
- and
- a pull down circuit connected to the level shifting circuit that sinks current from the inverted output when the level shifting circuit sinks current from the inverted output, and from the non-inverted output when the level shifting circuit sinks current from the non-inverted output;
- wherein the pull down circuit includes:
- a first transistor connected between the inverted output and ground;
- and
- a second transistor isolated from the inverted output, the second transistor being connected to the first transistor and the level shifting circuit to turn on the first transistor when the level shifting circuit sinks current from the inverted output.
A level shifter comprising:
- a level shifting circuit having an input, an inverted output, and a non-inverted output, a logic high at the input having a first voltage, a logic high at the inverted output having a second voltage, a logic high at the non-inverted output having the second voltage, the second voltage being greater than the first voltage;
- and
- a pull down circuit connected to the level shifting circuit that sinks current from the inverted output when the level shifting circuit sinks current from the inverted output, and from the non-inverted output when the level shifting circuit sinks current from the non-inverted output, the pull down circuit including:
- a first transistor connected between the inverted output and ground;
- and
- a second transistor isolated from the inverted output, the second transistor being connected to the first transistor and the level shifting circuit to turn on the first transistor when the level shifting circuit sinks current from the inverted output;
- a third transistor connected between the non-inverted output and ground;
- and
- a fourth transistor isolated from the non-inverted output, the fourth transistor being connected to the third transistor and the level shifting circuit to turn on the third transistor when the level shifting circuit sinks current from the non-inverted output.
Dependencies are inferred from the claim text.