Timing circuit for separate positive and negative edge placement in a switching DC-DC converter

A signal processing method, comprising:

• delaying a clock signal by a first amount to form a first delayed clock signal;
• delaying the clock signal by a second amount to form a second delayed clock signal;
• and
• generating a timing signal from the clock signal, the timing signal having a first edge controlled by the first delayed clock signal and a second edge controlled by the second delayed clock signal, wherein generating includes:
• forming an interim timing signal from the clock signal, the interim timing signal having edge transitions which coincide with one of a falling edge and a rising edge of the clock signal;
• and
• generating the timing signal from the interim timing signal, wherein the interim timing signal is periodic with a period which is substantially twice as long as the period of the clock signal.

A circuit, comprising:

• a switch;
• and
• a timing circuit to control input of a voltage signal through the switch, said timing circuit including:
• a first delay line to delay a clock signal by a first amount of time,
• a second delay line to delay the clock signal by a second amount of time, and
• a signal processor to generate a timing signal from the clock signal, the timing signal having a first edge controlled by the delayed clock signal generated by the first delay line and a second edge controlled by the delayed clock signal generated by the second delay line, wherein different portions of the timing signal independently control input of the voltage signal through the switch.

A method, comprising:

• delaying a clock signal by a first amount to form a first delayed clock signal;
• delaying the clock signal by a second amount to form a second delayed clock signal;
• generating a timing signal from the clock signal, the timing signal having a first edge controlled by the first delayed clock signal and a second edge controlled by the second delayed clock signal;
• and
• controlling input of a voltage signal into a level converter based on the timing signal, wherein different portions of the timing signal independently control switching of the voltage signal into the level converter.

A circuit, comprising:

• a first delay line to delay a clock signal by a first amount of time;
• a second delay line to delay the clock signal by a second amount of time;
• and
• a signal processor to generate:
• a) a first timing signal from the clock signal,
• b) a second timing signal having edge transitions controlled by the first timing signal at times determined by a logical combination of the delayed clock signals from the first and second delay lines, and
• c) a third timing signal having edge transitions controlled by the second timing signal at times determined by one of the delayed clock signals from the first and second delay lines, wherein the first timing signal has a period which is a number of times longer than the clock signal.

A comprising:

• a first delay line to delay a clock signal by a first amount of time;
• a second delay line to delay the clock signal by a second amount of time;
• and
• a signal processor to generate:
• a first timing signal from the clock signal,
• a second timing signal having edge transitions controlled by the first timing signal at times determined by a logical combination of the delayed clock signals from the first and second delay lines, and
• c) a third timing signal having edge transitions controlled by the second timing signal at times determined by one of the delayed clock signals from the first and second delay lines, wherein the signal processor includes:
• a first logical circuit to control the edge transitions of the second timing signal based on logical values of the first timing signal at times determined by a logical combination of the delayed clock signals, wherein the first logical circuit includes a data input coupled to receive the first timing signal and a clock input coupled to receive a signal indicative of a logical combination of the delayed clock signals.

A circuit comprising:

• a first delay line to delay a clock signal by a first amount of time;
• a second delay line to delay the clock signal by a second amount of time;
• a signal processor to generate:
• a) a first timing signal from the clock signal,
• b) a second timing signal having edge transitions controlled by the first timing signal at times determined by a logical combination of the delayed clock signals from the first and second delay lines, and
• c) a third timing signal having edge transitions controlled by the second timing signal at times determined by one of the delayed clock signals from the first and second delay lines;
• and
• a controller to change at least one of the first and second amounts of time in the delay lines, to adjust a position of at least one of the first and second edges of the third timing signal.

A system, comprising:

• a first circuit;
• and
• a second circuit coupled to the first circuit, the second circuit comprising:
• a) a first delay line to delay a clock signal by a first amount of time;
• b) a second delay line to delay the clock signal by a second amount of time;
• c) a signal processor to generate:
• a first timing signal from the clock signal,
• a second timing signal having edge transitions controlled by the first timing signal at times determined by a logical combination of the delayed clock signals from the first and second delay lines, and
• a third timing signal having edge transitions controlled by the second timing signal at times determined by one of the delayed clock signals from the first and second delay lines, wherein the timing signal controls operation of the first circuit, wherein the first timing signal has a period which is a number of times longer than the clock signal.