Apparatus and method for controlling a delay chain
AssigneeAltera Corporation
InventorsBonnie I. Wang, Joseph Huang, Chiakang Sung, Yan Chong, Khai Nguyen, Henry Kim
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Abstract
A method and apparatus for updating the control signal received by a delay chain in a DDR application. A register is used to regulate the control signal to the delay chain. The register only updates the signal at the delay chain when a signal is not passing through the delay chain. Additionally, the present invention is directed to a delay circuit that uses a plurality of PMOS and NMOS transistors connected in parallel to each other and to an inverter that provides the desired delay. The delay provided is achieved by sequentially turning off/on a series of the NMOS/PMOS transistor pairs.
Claims20
An integrated circuit comprising:
- a delay chain having a DQS input, a DQS output and a control signal input,
- a register connected to the delay chain, the register having an input for receiving the control signal and an output for transmitting the control signal to the delay chain, wherein
- if a DQS signal is passing through the delay chain, the register will ignore any changes to the input,
- if a DQS signal is not passing through the delay chain, the register will pass through any changes to the input.
A method of controlling a delay chain, the delay chain having an input signal, an output signal and a control signal, the method comprising:
- comparing an input and an output signal of the delay chain;
- determining if a signal is passing through the delay chain;
- and
- if a signal is passing through the delay chain, then not updating the control signal at the delay chain,
- if a signal is not passing through the delay chain, then updating the control signal at the delay chain.
Dependencies are inferred from the claim text.