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US 7,030,674 B2Granted
Multiphase clock generators
AssigneeMicron Technology, Inc.
InventorBrian Johnson
Life of this patent
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Abstract
Multiphase clock generators and methods are provided. A multiphase clock generator has a first clock divider for generating a first-phase clock signal from a first input clock signal. A first logic gate is connected to an output port of the first clock divider. A second clock divider is connected to an output port of the first logic gate. The second clock divider is for generating a second-phase clock signal from the first input clock signal. A second logic gate is connected to an output port of the second clock divider. A third clock divider is connected to an output port of the second logic gate. The third clock divider is for generating a third-phase clock signal from a second input clock signal.
Claims35
A multiphase clock generator, comprising:
- a first clock divider having a first input for receiving a first input clock signal, a second input for receiving a reset signal and an output for providing a first output clock signal;
- a second clock divider having a first input for receiving the first input clock signal, a second input for receiving a reset signal and an output for providing a second output clock signal;
- a third clock divider having a first input for receiving a second input clock signal, a second input for receiving a reset signal and an output for providing a third output clock signal;
- and
- a fourth clock divider having a first input for receiving the second input clock signal, a second input for receiving a reset signal and an output for providing a fourth output clock signal;
- wherein the reset signal for the first clock divider is generated from a first reset signal;
- wherein the reset signal for the second clock divider is generated from the first reset signal and the first output clock signal;
- wherein the reset signal for the third clock divider is generated from the first reset signal, the second output clock signal and the second input clock signal;
- and
- wherein the reset signal for the fourth clock divider is generated from the first reset signal and the third output clock signal.
7 more elements
A method of operating a multiphase clock generator, the method comprising:
- placing first, second, third and fourth clock dividers in a reset state in response to a first reset signal having a first logic level, wherein the first and second clock dividers are coupled to receive a first input clock signal and the third and fourth clock dividers are coupled to receive a second input clock signal, and wherein outputs of the first, second, third and fourth clock dividers assume a logic low level in their reset states;
- starting the first clock divider from its reset state in response to the first reset signal transitioning to a second logic level;
- starting the second clock divider from its reset state in response to the first reset signal transitioning to its second logic level and the output of the first clock divider transitioning to a logic high level;
- starting the third clock divider from its reset state in response to the second input clock signal having a logic high level and the output of the second clock divider transitioning to a logic high level;
- and
- starting the fourth clock divider from its reset state in response to the first reset signal transitioning to its second logic level and the output of the third clock divider transitioning to a logic high level.
3 more elements
A method of operating a multiphase clock generator, the method comprising:
- resetting a plurality of clock dividers in response to a first reset signal having a first logic level, wherein each clock divider is coupled to receive an input clock signal and a reset signal, wherein each clock divider is adapted to provide an output clock signal having a first logic level or a second logic level during operation, and wherein each output clock signal assumes its first logic level when its corresponding clock divider assumes its reset state;
- transitioning the first reset signal to a second logic level;
- starting a first clock divider from its reset state in response to the first reset signal transitioning to its second logic level and a first input clock signal transitioning from a first logic level to a second logic level;
- starting a second clock divider from its reset state in response to the first reset signal transitioning to its second logic level, the output clock signal of the first clock divider transitioning to its second logic level and the first input clock signal transitioning to its second logic level;
- starting a third clock divider from its reset state in response to the output clock signal of the second clock divider transitioning to its second logic level and a second input clock signal transitioning from a first logic level to a second logic level;
- and
- starting a fourth clock divider from its reset state in response to the first reset signal transitioning to its second logic level, the output clock signal of the third clock divider transitioning to its second logic level and the second input clock signal transitioning to its second logic level.
4 more elements
Dependencies are inferred from the claim text.