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US 7,030,673 B2Granted
Phase splitter circuit
AssigneeSamsung Electronics Co., Ltd.
InventorKi-Whan Song
Life of this patent
Estimating the term…
Abstract
A phase splitter circuit includes a first signal generator and a second signal generator. The first signal generator generates a first signal in response to an input signal. The second signal generator generates a second signal in response to the input signal. The phase of the first signal is different from that of the first signal. In particular, the phase splitter circuit has a means that is capable of controlling the first and second signals such that transition times thereof are equal. As a result, the phase splitter circuit may fulfill not only delay matching of each element, but also equality of the transition times of output signals.
Claims38
A phase splitter circuit comprising:
- a first signal transfer path for receiving an input signal to generate a first output signal of which phase is equal to that of the input signal;
- and
- a second signal transfer path for receiving the input signal to generate a second output signal that is an inverted version of the first output signal,
- wherein each of the first and second signal transfer paths includes a plurality of cascaded logic elements, and each of which has pull-up and pull-down delay times,
- wherein when the input signal makes a transition, the sum of pull-down delay times of elements of the first signal transfer path is equal to the sum of pull-down delay times of elements of the second signal transfer path, and the sum of pull-up delay times of elements of the first signal transfer path is equal to the sum of pull-up delay times of elements of the second signal transfer path, and
- wherein a transition time of the first output signal is equal to a transition time of the second output signal.
3 more elements
A phase splitter circuit comprising:
- an input node;
- a first signal generating unit adapted to receive an input signal from the input node to generate a first output signal having a phase that is equal to that of the input signal;
- and
- a second signal generating unit adapted to receive the input signal from the input node to generate a second output signal, an inverted version of the first output signal,
- wherein the first and second signal generating units are optimized such that a transition time of the first output signal is equal to a transition time of the second output signal.
2 more elements
A phase splitter circuit comprising:
- an input node;
- a first signal generator connected to the input node and adapted to generate a first signal in response to an input signal applied to the input node;
- and
- a second signal generator connected to the input node and adapted to generate, in response to the input signal, a second signal having a phase that is different from that of the first signal,
- wherein the phase splitter circuit includes a means for adjusting a transition time of the first signal so that the first signal has the same transition time as that of the second signal.
2 more elements
A phase splitter circuit comprising:
- an input node;
- a first signal generator connected to the input node and adapted to generate a first signal in response to an input signal applied to the input node;
- and
- a second signal generator connected to the input node and adapted to generate, in response to the input node, a second signal having a phase that is different from that of the first signal,
- wherein the first signal generator includes a first means for adjusting a transition time of the first signal so that the first signal may have the same transition time as that of the second signal, and
- wherein the second signal generator includes a second means for compensating delay elements of the first signal, optimized according to a delay matching method varied by the first means.
3 more elements
A phase splitter circuit comprising:
- an input node;
- a first output node;
- a second output node;
- a first signal generator adapted to generate a first internal clock signal in response to an external clock signal applied to the input node, wherein the first signal generator includes a first current-starved inverter and a first CMOS inverter that are connected in cascade between the input node and the first output node;
- and
- a second signal generator adapted to generate a second internal clock signal in response to an external clock signal applied to the input node, wherein the second signal generator includes a second CMOS inverter, a second current-starved inverter, and a third CMOS inverter that are connected in cascade between the input node and the second output node.
3 more elements
A phase splitter circuit comprising:
- an input node;
- a first output node;
- a second output node;
- a first signal generator adapted to generate a first internal clock signal in response to an external clock signal applied to the input node, wherein the first signal generator includes a first current-starved inverter and a first CMOS inverter that are connected in cascade between the input node and the first output node;
- and
- a second signal generator adapted to generate a second internal clock signal in response to an external clock signal applied to the input node, wherein the second signal generator includes a second CMOS inverter, a second current-starved inverter, and a third CMOS inverter that are connected in cascade between the input node and the second output node,
- wherein each of the first and second current-starved inverters includes first and second PMOS transistors, and first and second NMOS transistors, and
- wherein in each of the first and second current-starved invertors, the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are connected in cascade between first and second power lines in this order.
5 more elements
A phase splitter circuit comprising:
- an input node;
- a first output node;
- a second output node;
- a first signal generator adapted to generate a first internal clock signal in response to an external clock signal applied to the input node, wherein the first signal generator includes a first current-starved inverter and a first CMOS inverter that are connected in cascade between the input node and the first output node;
- and
- a second signal generator adapted to generate a second internal clock signal in response to an external clock signal applied to the input node, wherein the second signal generator includes a second CMOS inverter, a second current-starved inverter, and a third CMOS inverter that are connected in cascade between the input node and the second output node,
- wherein each of the first and second current-starved inverters includes a first resistor, a PMOS transistor, a NMOS transistor, and a second resistor, and
- wherein in each of the first and second current-starved inventors, the first resistor, the PMOS transistor, the NMOS transistor, and the second resistor are connected in cascade between first and second power lines in this order.
5 more elements
Dependencies are inferred from the claim text.