Adiabatic charging register circuit

A CMOS register circuit having a plurality of n-channel MOSFET transistors and a plurality of p-channel MOSFET transistors, accepting an input data, and a clock signal, and providing an output data, said clock signal not being a conventional CMOS signal and instead being a charge recycled clock signal having a stepwise waveform from a switched capacitor regenerator in which power supplied to a load is at least partially collected to said switched capacitor regenerator, and

• the following inequality is satisfied for getting rid of short circuit current:
• |VTN|+|VTP|≧VDD
• where VTN is a threshold of said n-channel MOSFET transistor, VTP is a threshold of said p-channel MOSFET, and VDD is an output voltage of said switched capacitor regenerator,
• wherein said register circuit comprises a pair of D-latch circuits with an input of a second D-latch circuit coupled with an output of a first D-latch circuit, a first D-latch circuit accepts a first stepwise waveform clock signal, and a second D-latch circuit accepts a second stepwise waveform clock signal which is different by 180° phase of the first power clock signal.