Circuit for controlling pulse width

A circuit for controlling a pulse width, comprising:

• a plurality of delay units for each respectively delaying a clock for a different time;
• a plurality of flip-flops for generating a plurality of detection signals by comparing the clock with output signals from the plurality of delay units, respectively;
• a plurality of encoding means for generating a plurality of mode signals by encoding the plurality of detection signals from the plurality of flip-flops;
• a pulse generation unit for generating a pulse according to a plurality of control signals;
• a latch for latching the pulse generated in the pulse generation unit, which is connected to an output terminal of the pulse generation unit;
• a pulse width control unit for controlling the pulse width by receiving an output signal from the latch and delaying the signal according to the plurality of mode signals;
• and
• a logical means for receiving the output signal from the latch and an output signal from the pulse width control unit.