Line driver

A line driver for data transmission comprising a plurality of driver stages, each driver stage comprising:

• a first transistor pair with first and second transistors which are differentially actuated as a function of the data which is to be transmitted;
• and
• a second transistor pair with a first and second cascade transistor, the first cascade transistor of the second transistor pair connected in series between the first transistor of the first transistor pair of the same driver stage and a first output of the line driver, and the second cascade transistor connected in series between the second transistor of the first transistor pair of the same driver stage and a second output of the line driver, in such a way that the individual driver stages are connected in each case in parallel via the corresponding second transistor pair to the first and second outputs of the line driver;
• a control circuit allocated to each driver stage for creating differential control signals (VGA, VGB) to actuate the two transistors of the first transistor pair of the individual driver stage, whereby each control circuit is designed in such a way that, when the differential control signals (VGA, VGB) are created, a specific maximum current flows via the one transistor of the first transistor pair, and a specific minimum current flows via the other transistor of the first transistor pair;
• wherein each control circuit is designed in such a way that it can adjust the common mode level of the control signals (VGA, VGB) created to actuate the two transistors of the first transistor pair of the individual driver stage, independently of the signal level swing of these control signals (VGA, VGB).

A line driver for data transmission comprising a plurality of driver stages, each driver stage comprising:

• a first transistor pair with first and second transistors which are differentially actuated as a function of the data which is to be transmitted;
• and
• a second transistor pair with a first and second cascade transistor, the first cascade transistor of the second transistor pair connected in series between the first transistor of the first transistor pair of the same driver stage and a first output of the line driver, and the second cascade transistor connected in series between the second transistor of the first transistor pair of the same driver stage and a second output of the line driver, in such a way that the individual driver stages are connected in each case in parallel via the corresponding second transistor pair to the first and second outputs of the line driver;
• a control circuit allocated to each driver stage for creating differential control signals (VGA, VGB) to actuate the two transistors of the first transistor pair of the individual driver stage, whereby each control circuit is designed in such a way that, when the differential control signals (VGA, VGB) are created, a specific maximum current flows via the one transistor of the first transistor pair, and a specific minimum current flows via the other transistor of the first transistor pair;
• wherein each control circuit comprises a pair of transfer gates, whereby each transfer gate is actuated by complementary control signals (DW, DW′) as a function of the data which is to be transmitted, and optionally forwards, or not, a current (Isig) from a current source as a function of the actuation by these control signals (DW, DW′), to a voltage divider formed by switching elements with a linear voltage/current characteristic curve, whereby at the one voltage divider the control signal (VGB) is provided for the actuation of the first transistor, and at the other voltage divider the control signal (VGA) is provided for the actuation of the second transistor of the first transistor pair of the corresponding driver stage.

A line driver for data transmission comprising a plurality of driver stages, each driver stage comprising:

• a first transistor pair with first and second transistors which are differentially actuated as a function of the data which is to be transmitted;
• and
• a second transistor pair with a first and second cascade transistor, the first cascade transistor of the second transistor pair connected in series between the first transistor of the first transistor pair of the same driver stage and a first output of the line driver, and the second cascade transistor connected in series between the second transistor of the first transistor pair of the same driver stage and a second output of the line driver, in such a way that the individual driver stages are connected in each case in parallel via the corresponding second transistor pair to the first and second outputs of the line driver;
• wherein the cascade transistors of the second transistor pair of each driver stage ate subjected to a bias voltage by a corresponding voltage source, which is connected to the individual cascade transistor to the second transistor pair in each case by means of a bias voltage line, whereby the bias voltage line allocated to each cascade transistor of the second transistor pair is couples to a capacitor.