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US 7,030,655 B2Granted
Memory interface system
AssigneeSamsung Electronics Co., Ltd.
InventorJung-Hwan Choi
Life of this patent
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Abstract
The invention relates to a semiconductor memory device and, more particularly, to an interface system for a semiconductor memory device. The interface includes a transmitter capable of encoding first and second input signals as a plural-bit symbol signal responsive to first and second clocks, respectively, the first clock being out of phase from the second clock. And the interface includes a receiver capable of generating first and second output signals by decoding the symbol signal responsive to third and fourth clocks, respectively. Other embodiments are illustrated and described.
Claims25
A semiconductor device comprising:
- a transmitter capable of encoding first and second input signals as a plural-bit symbol signal responsive to first and second clocks, respectively, the first clock being out of phase from the second clock;
- and
- a receiver capable of generating first and second output signals by decoding the symbol signal responsive to third and fourth clocks, respectively, and capable of generating first and second even and odd data;
- where the receiver comprises:
- a first receiving circuit capable of generating the first output signal by manipulating the symbol signal responsive to the third and a fifth clocks, the fifth clock being out of phase from the third clock, the first receiving circuit being adapted to generate the first even and odd data responsive to the third and fifth clocks, respectively;
- and
- a second receiving circuit capable of generating the second output signal by manipulating the symbol signal responsive to the fourth and a sixth clocks, the sixth clock being out of phase from the fourth clock, the second receiving circuit being adapted to generate the second even and odd data responsive to the fourth and sixth clocks, respectively;
- and
- where the first receiving circuit comprises:
- a first detector capable of generating the first even and odd data according to a medium reference voltage;
- a second detector capable of generating first select signal by detecting midlevel data according to high and low reference voltages;
- and
- a multiplexer capable of selecting between the first even and the second odd data and the first odd and the second even data responsive to the select signal.
10 more elements
A semiconductor device comprising:
- a transmitter capable of encoding first and second input signals as a plural-bit symbol signal responsive to first and second clocks, respectively, the first clock being out of phase from the second clock;
- and
- a receiver capable of generating first and second output signals by deciding the symbol signal responsive to third and fourth clocks, respectively, and capable of generating first and second even and odd data;
- where the receiver comprises:
- a first receiving circuit capable of generating the first output signal by manipulating the symbol signal responsive to the third and a fifth clocks, the fifth clock being out of phase from the third clock, the first receiving circuit being adapted to generate the first even and odd data responsive to the third and fifth clocks, respectively;
- and
- a second receiving circuit capable of generating the second output signal by manipulating the symbol signal responsive to the fourth and a sixth clocks, the sixth clock being out of phase from the fourth clock, the second receiving circuit being adapted to generate the second even and odd data responsive to the fourth and sixth clocks, respectively;
- and
- where the second receiving circuit comprises:
- a first detector capable of generating the second even and odd data according to a medium reference voltage;
- a second detector capable of generating a select signal by detecting midlevel data according to high and low reference voltages;
- and
- a multiplexer capable of selecting between the first and second even data and the first and second odd data responsive to the select signal.
10 more elements
A device, comprising:
- transmitting means capable of encoding input data as plural-bit symbol data responsive to at least two transmitting clocks out of phase from each other;
- and
- receiving means capable of generating output data and first and second even and odd data by decoding the symbol data responsive to at least two receiving clocks;
- where the receiving means comprises:
- first receiving circuit means capable of generating first output data by manipulating the symbol data responsive to one of the at least two receiving clocks:
- and
- second receiving circuit means capable of generating second output data by manipulating the symbol data responsive to another of the at least two receiving clocks;
- where the first receiving circuit means comprises:
- first detecting means capable of generating first pre even and pre odd data according to a medium reference voltage;
- second detecting means capable of generating the first odd and even select signals by detecting midlevel data according to high and low reference voltages;
- and
- first multiplexing means capable of selecting between the first pre even and pre odd data and second even and odd data responsive to the first odd and even select signals, respectively.
9 more elements
A receiver, comprising:
- a first receiving circuit capable of generating first output data and first even and odd data by manipulating symbol data responsive to a first and second clocks, the first output data being single bit data, the symbol data being plural-bit data, the first receiving circuit being capable of receiving the second even and odd data;
- and
- a second receiving circuit capable of generating second output data and second even and odd data by manipulating the symbol data responsive to a third and fourth clocks, the second output data being single bit data, the second receiving circuit being capable of receiving the first even and odd data;
- where the second clock is out of phase from the first clock and the fourth clock is out of phase from the third clock;
- and
- where the first receiving circuit comprises:
- a first detector capable of generating first pre odd and pre even data responsive to a medium reference voltage;
- a second detector capable of generating first odd and even select signals by detecting midlevel data responsive to high and low reference voltages;
- and
- a multiplexer capable of selecting between the first pre even data and the second odd data responsive to the first even select signal and between the first pre odd data and the second even data responsive to the first odd select signal.
7 more elements
Dependencies are inferred from the claim text.