Low voltage to extra high voltage level shifter and related methods

A shifter circuit comprising:

• a matched translation stack comprising first and second stacks each of which comprising multiple p-channel MOSFETs and n-channel MOSFETs, the first stack being connected between a voltage level to which a shift is desired (VddH) and a voltage level away from which the shift is desired (VddL), the second stack being connected between the voltage level to which a shift is desired (VddH) and an input signal Vin, the matched translation stack being configured to provide a primary logic level shift;
• multiple cascaded high voltage buffer stages, a first of which being connected with and biased by the first stack of the matched translation stack, said high voltage buffer stages each comprising:
• multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack, said multiple transistors being connected to receive, if said high voltage buffer stage is the first high voltage buffer stage, an input supplied by said second stack of the matched translation stack and, if said high voltage buffer stage is not said first high voltage buffer stage, an input provided by an output of a preceding high voltage buffer stage;
• and
• an inverter comprising multiple inputs and an output, individual inverter inputs being connected to a respective intermediate node of the transistor stack;
• multiple cascaded low voltage buffer stages having an input and an output, a first of the low voltage buffer stages being connected to the input signal Vin, and being connected between the voltage level away from which the shifted is desired (VddL) and a lower voltage;
• and
• an output buffer stage driven by the outputs of the high voltage buffer stage and the low voltage buffer stage.

A method comprising:

• supplying a voltage level away from which a shift is desired (VddL);
• supplying a voltage level to which a shift is desired (VddH);
• supplying an input voltage Vin;
• and
• shifting the input voltage, using said voltage levels and a circuit comprising:
• a matched translation stack comprising at least first and second stacks each of which comprising multiple transistors, the matched translation stack being configured to provide a primary logic level shift between the voltage level away from which the shift is desired (VddL) and the voltage level to which the shift is desired (VddH);
• one or more high voltage buffer stages at least one of which being connected with and biased by the matched translation stack, said at least one high voltage buffer stage comprising:
• multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack, the transistor stack being biased by said first stack of the matched translation stack, and being connected to receive an input supplied by said second stack of the matched translation stack;
• and
• an inverter comprising multiple inputs and an output, individual inverter inputs being connected to a respective intermediate node of the transistor stack;
• a low voltage buffer stage having an input and an output, the input being connected to the input voltage Vin, and being connected between the voltage level away from which the shifted is desired (VddL) and a lower voltage;
• and
• an output buffer stage driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.