Programmable structured arrays

A semiconductor device for integrated circuits with two selectable manufacturing configurations, comprising:

• a first module layer having an array of structured cells, said module layer having at least one layer of metal;
• and
• a second module layer formed substantially above said first module layer comprising two selectable configurations, wherein:
• in a first selectable configuration a programmable interconnect structure is formed to connect said structured cells, and
• in a second selectable configuration a customized interconnect structure is formed to connect said structured cells;
• wherein, said programmable interconnect structure is further comprised of a user configurable memory circuit constructed on a thin film layer comprising one of fuse links, anti-fuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electro-chemical elements, optical elements and magnetic elements;
• and
• wherein, said customized interconnect structure is further comprised of ((a)) conductive pattern comprising fabricating hard wire controls to replicate a specific memory pattern, wherein replicating comprises:
• a logic zero memory output mapped to a hard wire disconnect;
• and
• a logic one memory output mapped to a hard wire connect.