High performance interconnect architecture for field programmable gate arrays
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsAnkur Bal, Namerita Khanna
Life of this patent
Estimating the term…
Abstract
This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.
Claims20
A high performance interconnect architecture for a field programmable gate array (FPGA), comprising a plurality of tiles, each tile comprising:
- a plurality of logic blocks, each of which can be selectively connected to one or more logic blocks separated from it by one or more intervening logic blocks,
- a plurality of interconnect segments, each of which connects two or more logic blocks and is routed in a straight line through an interconnect layer over the one or more intervening logic blocks, and
- a connecting segment provided at a periphery within each logic block for selectively connecting the logic block with one of the interconnect segments.
A method for providing a high performance interconnect architecture for a field programmable gate array (FPGA), comprising the steps of:
- providing a plurality of tiles,
- providing a plurality of logic blocks within each tile,
- enabling selective connection between a plurality of the logic blocks separated from each other by one or more intervening logic blocks,
- routing a plurality of interconnect segments, each interconnect segment routed between two connected logic blocks in a straight line through an interconnect layer over the one or more intervening logic blocks, and
- providing a connecting segment at a periphery of each logic block for selective connection of the logic block with one of the interconnect segments.
A field programmable gate array comprising a plurality of tiles, at least one of the tiles comprising:
- a plurality of logic blocks, each logic block capable of being connected to one or more non-adjacent logic blocks;
- a plurality of interconnect segments, each interconnect segment routed in a straight line over one or more intervening logic blocks between two connected logic blocks;
- and
- at least one connecting segment, each connecting segment capable of connecting one of the logic blocks to one of the interconnect segments.
Dependencies are inferred from the claim text.