Techniques for configuring programmable logic using on-chip nonvolatile memory

A method of operating a programmable logic integrated circuit comprising:

• after providing power to the integrated circuit, starting a timer circuit to provide a time count value;
• in a first state, reading a first pattern stored at a first address from a nonvolatile configuration memory of the programmable logic integrated circuit;
• if the time count value is a max count value, disabling transfer of configuration data from the nonvolatile configuration memory to the programmable logic core;
• if the time count value is not the max count value, in a second state, comparing the first pattern to an expected first pattern and returning to the first state if the first pattern does not match the expected first pattern;
• if the first pattern matches the expected first pattern, continuing to a third state, reading a second pattern stored at a second address from the nonvolatile configuration memory of the programmable logic integrated circuit;
• and
• following the third state, in a fourth state, comparing the second pattern to an expected second pattern and returning to the first state if the second pattern does not match the expected second pattern.

A method of operating a programmable logic integrated circuit comprising:

• after providing power to the integrated circuit, in a first state, reading a first pattern stored at a first address from a nonvolatile configuration memory of the programmable logic integrated circuit;
• following the first state, in a second state, comparing the first pattern to an expected first pattern and returning to the first state if the first pattern does not match the expected first pattern;
• if the first pattern matches the expected first pattern, continuing to a third state, reading a second pattern stored at a second address from the nonvolatile configuration memory of the programmable logic integrated circuit;
• following the third state, in a fourth state, comparing the second pattern to an expected second pattern and returning to the first state if the second pattern does not match the expected second pattern;
• if the second pattern matches the expected second pattern, permitting configuration of a programmable logic core of the programmable logic integrated circuit using configuration data stored in the nonvolatile configuration memory;
• transferring in parallel a user's configuration data stored in the configuration memory to the programmable logic core of the programmable logic integrated circuit;
• verifying the transfer of the user's configuration data by reading and comparing at least two additional bits of each word of the parallel transfer to expected results for these two additional bits;
• and
• restarting the transfer of the user's configuration data if the at least two additional bits do not match the expected results for the two additional bits.