US 7,030,643 B2Granted

Output buffer circuits including logic gates having balanced output nodes

AssigneeSamsung Electronics Co., Ltd.

InventorJoung-yeal Kim

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Abstract

A buffer circuit may include an output terminal, a pull-up transistor, a pull-down transistor, and first and second logic gates. The pull-up transistor is connected between the output terminal and a supply voltage, and the pull-up transistor pulls the output terminal up to the supply voltage responsive to a pull-up control signal. The pull-down transistor is connected between the output terminal and a reference voltage, and the pull-down transistor pulls the output terminal down to the reference voltage responsive to a pull-down control signal. The first logic gate may generate the pull-up control signal at a first output node responsive to a control signal and a data signal, and the first logic gate may include a plurality of serially connected transistors in an electrical path between the supply voltage and the first output node. The second logic gate may generate the pull-down control signal at a second output node responsive to the data signal and an inverse of the control signal, and the second logic gate may include a plurality of serially connected transistors in a path between the supply voltage and the second output node.

Claims30

Dependent claims

A buffer circuit comprising;

an output terminal;
a pull-up transistor connected between the output terminal and a supply voltage, wherein the pull-up transistor pulls the output terminal up to the supply voltage responsive to a pull-up control signal;
a pull-down transistor connected between the output terminal and a reference voltage, wherein the pull-down transistor pulls the output terminal down to the reference voltage responsive to a pull-down control signal;
a first logic gate configured to generate the pull-up control signal at a first output node responsive to a control signal and a data signal, and wherein the first logic gate includes a plurality of serially connected transistors in an electrical path between the supply voltage and the first output node;
and
a second logic gate configured to generate the pull-down control signal at a second output node responsive to the data signal and an inverse of the control signal and wherein the second logic gate includes a plurality of serially connected transistors in a path between the supply voltage and the second output node;
wherein the number of serially connected transistors in the path between the supply voltage and the first output node is equivalent to the number of serially connected transistors in the path between the supply voltage and the second output node;
wherein the plurality of serially connected transistors in the electrical path between the supply voltage and the first output node comprises a first transistor having a first control electrode connected to the data signal and a second transistor coupled in series between the supply voltage and the first transistor, the first logic gate further comprising a third transistor connected in parallel with the first transistor between the second transistor and the first output node, wherein the third transistor has a third control electrode connected to the control signal.

5 more elements

An output buffer comprising;

an output terminal;
a pull-up transistor connected between the output terminal and a supply voltage, wherein the pull-up transistor pulls the output terminal up to the supply voltage responsive to a pull-up control signal;
a pull-down transistor connected between the output terminal and a reference voltage, wherein the pull-down transistor pulls the output terminal down to the reference voltage responsive to a pull-down control signal;
a first logic gate configured to generate the pull-up control signal at a first output node responsive to a control signal and a data signal, and wherein the first logic gate includes a plurality of serially connected transistors in a path between the first output node and the reference voltage;
and
a second logic gate configured to generate the pull-down control signal at a second output node responsive to the data signal and an inverse of the control signal and wherein the second logic gate includes a plurality of serially connected transistors in a path between the second output node and the reference voltage;
wherein the number of serially connected transistors in the path between the first output node and the reference voltage is equivalent to the number of serially connected transistors in the path between the second output node and the reference voltage;
wherein the plurality of serially connected transistors in the electrical path between the second output node and the reference voltage comprises a first transistor having a first control electrode connected to the data signal and a second transistor connected in series between the first transistor and the reference voltage, the second logic gate further comprising a third transistor connected in parallel with the first transistor between the second transistor and the second output node, wherein the third transistor has a control electrode connected to the inverse of the control signal.

5 more elements

An output buffer circuit comprising:

a pull-up transistor which pulls up an output terminal in response to a pull-up control signal;
a pull-down transistor which pulls down the output terminal in response to a pull-down control signal;
a NAND gate which receives at least one control signal and data and generates the pull-up control signal;
and
a NOR gate which receives an inverted signal of the control signal and the data and generates the pull-down control signal, wherein a number of PMOS transistors present along a path of a first supply voltage to an output terminal of the NAND gate is equivalent to a number of PMOS transistors present along a path of the first supply voltage to an output terminal of the NOR gate, and a number of NMOS transistors present along a path of a second supply voltage to an output terminal of the NAND gate is equivalent to a number of NMOS transistors present along a path of the second supply voltage to an output terminal of the NOR gate;
wherein the NAND gate comprises,
a first PMOS transistor which has a source to which the first supply voltage is applied and a gate to which the second supply voltage is applied,
a second PMOS transistor which has a source connected to a drain of the first PMOS transistor, a gate to which the data is input, and a drain connected to the output terminal of the NAND gate,
a third PMOS transistor which has a source connected to the drain of the first PMOS transistor, a gate to which the control signal is applied, and a drain connected to the output terminal of the NAND gate,
a first NMOS transistor which has a drain connected to the output terminal of the NAND gate and a gate to which the data is input, and
a second NMOS transistor which has a drain connected to a source of the first NMOS transistor, a gate to which the control signal is applied, and a source to which the second supply voltage is applied.

8 more elements

An output buffer circuit comprising:

a pull-up transistor which pulls up an output terminal in response to a pull-up control signal;
a pull-down transistor which pulls down the output terminal in response to a pull-down control signal;
a NAND gate which receives at least one control signal and data and generates the pull-up control signal;
and
a NOR gate which receives an inverted signal of the control signal and the data and generates the pull-down control signal,
wherein a number of PMOS transistors present along a path of a first supply voltage to an output terminal of the NAND gate is equivalent to a number of PMOS transistors present along a path of the first supply voltage to an output terminal of the NOR gate, and a number of NMOS transistors present along a path of a second supply voltage to an output terminal of the NAND gate is equivalent to a number of NMOS transistors present along a path of the second supply voltage to an output terminal of the NOR gate;
wherein the NAND gate comprises,
a first PMOS transistor which has a source to which the first supply voltage is applied and a gate to which the second supply voltage is applied,
a second PMOS transistor which has a source connected to the drain of the first PMOS transistor and a gate to which the second supply voltage is applied,
a third PMOS transistor which has a source connected to the drain of the second PMOS transistor, a gate to which the data is input, and a drain connected to the output terminal of the NAND gate,
a fourth PMOS transistor which has a source connected to the drain of the second PMOS transistor, a gate to which a first control signal is applied, and a drain connected to the output terminal of the NAND gate,
a fifth PMOS transistor which has a source connected to the drain of the second PMOS transistor, a gate to which a second control signal is applied, and a drain connected to the output terminal of the NAND gate,
a first NMOS transistor which has a drain connected to the output terminal of the NAND gate and a gate to which the data is input,
a second NMOS transistor which has a drain connected to a source of the first NMOS transistor and a gate to which the first control signal is applied, and
a third NMOS transistor which has a drain connected to a source of the second NMOS transistor, a gate to which the second control signal is applied, and a source to which the second supply voltage is applied.

12 more elements

An output buffer circuit comprising:

a pull-up transistor which pulls up an output terminal in response to a pull-up control signal;
a pull-down transistor which pulls down the output terminal in response to a pull-down control signal;
a NAND gate which receives at least one control signal and data and generates the pull-up control signal;
and
a NOR gate which receives an inverted signal of the control signal and the data and generates the pull-down control signal,
wherein a number of PMOS transistors present along a path of a first supply voltage to an output terminal of the NAND gate is equivalent to a number of PMOS transistors present along a path of the first supply voltage to an output terminal of the NOR gate, and a number of NMOS transistors present along a path of a second supply voltage to an output terminal of the NAND gate is equivalent to a number of NMOS transistors present along a path of the second supply voltage to an output terminal of the NOR gate;
wherein the NOR gate comprises,
a first PMOS transistor which has a source to which the first supply voltage is applied and a gate to which the data is input,
a second PMOS transistor which has a source connected to a drain of the first PMOS transistor and a gate to which an inverted signal of the first control signal is applied,
a third PMOS transistor which has a source connected to a drain of the second PMOS transistor, a gate to which an inverted signal of the second control signal is applied, and a drain connected to the output terminal of the NOR gate,
a first NMOS transistor which has a drain connected to the output terminal of the NOR gate and a gate to which the data is input,
a second NMOS transistor which has a drain connected to the output terminal of the NOR gate and a gate to which an inverted signal of the first control signal is applied,
a third NMOS transistor which has a drain connected to the output terminal of the NOR gate and a gate to which an inverted signal of the second control signal is applied,
a fourth NMOS transistor which has a drain connected to sources of the first through third NMOS transistors and a gate to which the first supply voltage is applied, and
a fifth NMOS transistor which has a drain connected to a source of the fourth NMOS transistor, a gate to which the first supply voltage is applied, and a source to which the second supply voltage is applied.

12 more elements

Dependencies are inferred from the claim text.