Substrate for semiconductor package and wire bonding method using thereof

A substrate for a semiconductor package comprising:

• an insulative layer;
• a solder mask on a surface of the insulative layer, wherein the solder mask includes a plurality of openings;
• a die attachment region formed on the surface of the insulative layer;
• a first conductive ring formed on the surface of the insulative layer outward of the die attachment region, wherein a portion of the first conductive ring is exposed through a respective one of the openings;
• a second conductive ring formed on the surface of the insulative layer outward of the first conductive ring, wherein a portion of the second conductive ring is exposed through a respective one of the openings;
• a plurality of electrically conductive patterns formed on the surface of the insulative layer outward of the second conductive ring, wherein each of the electrically conductive patterns includes a respective one of a plurality of bond fingers and an internal area of each of the bond fingers is individually exposed through a respective one of the openings;
• and
• a first reference mark formed on the surface of the insulative layer between the first conductive ring and the second conductive ring, the first reference mark comprising:
• one of the openings of the solder mask comprising a first region and a second region, which have a substantially oblong rectangular shape in a plan view and are connected at a substantially right angle;
• and
• a reference pattern comprising a first region and a second region, which have a substantially oblong rectangular shape in a plan view and are connected at a substantially right angle,
• wherein the first regions of the reference pattern and the solder mask opening cross each other perpendicularly;
• and
• wherein the second regions of the reference pattern and the solder mask opening also cross each other perpendicularly.

A substrate for a semiconductor package comprising:

• an insulative layer;
• a solder mask on a surface of the insulative layer, wherein the solder mask includes a plurality of openings;
• a die attachment region formed on the surface of the insulative layer;
• a first conductive ring formed on the surface of the insulative layer outward of the die attachment region, wherein a portion of, the first conductive ring is exposed through a respective one of the openings;
• a second conductive ring formed on the surface of the insulative layer outward of the first conductive ring, wherein a portion of the second conductive ring is exposed through a respective one of the openings;
• a plurality of electrically conductive patterns formed on the surface of the insulative layer outward of the second conductive ring, wherein each of the electrically conductive patterns includes a respective one of a plurality of bond fingers and an internal area of each of the bond fingers is individually exposed through a respective one of the openings;
• a first reference mark formed on the surface of the insulative layer between the first conductive ring and the second conductive ring;
• and
• a second reference mark formed on the surface of the insulative layer between the first conductive ring and the second conductive ring, the second reference mark diagonally opposed from the first reference mark.