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US 7,030,479 B2Granted
Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
AssigneeIntel Corporation
InventorsWilliam M. Siu, Bidyut K. Bhattacharyya
Life of this patent
Estimating the term…
Abstract
An integrated circuit die and/or package. An apparatus is described having a substrate with a central region and an outer region. A first plurality of electrical connections is spaced apart by a first distance on the outer region of the substrate. A second plurality of electrical connections is spaced apart by a second distance, smaller than the first distance, on the central region of the substrate.
Claims14
A printed circuit board comprising:
- a substrate having a surface, said surface having a central region and an outer region;
- and
- a first plurality of rows of electrical connections on said surface, each of said rows extending from the central region to the outer region;
- wherein a space between every pair of adjacent rows of the first plurality of rows is progressively larger from the central region to the outer region to contain a progressively increasing number of conductive traces, said space containing no electrical connections;
- wherein none of the electrical connections in each row are directly connected to one another electrically.
2 more elements
A printed circuit board comprising:
- an integrated circuit die having a surface, said surface having a central region and an outer region;
- and
- a first plurality of rows of electrical connections on said surface, each of said rows extending from the central region to the outer region;
- a space between each adjacent row, each of the spaces containing no electrical connections;
- wherein an average of all the spaces is progressively non-decreasing from the central region to the outer region.
2 more elements
A printed circuit board comprising:
- a substrate having a first surface, said first surface having a central region and an outer region;
- a first plurality of rows of electrical connections on said first surface, each of said rows extending from the central region to the outer region, wherein a space between ones of the electrical connections at substantially a same distance from the central region of the first plurality of rows is progressively larger from the central region to the outer region, said space containing no electrical connections;
- and a semiconductor die coupled to the substrate and having a second plurality of rows of electrical connections.
Dependencies are inferred from the claim text.