Semiconductor package containing an integrated-circuit chip supported by electrical connection leads
AssigneeSTMicroelectronics S.r.l.
InventorPatrick Perillat
Life of this patent
Estimating the term…
Abstract
Semiconductor package containing an integrated-circuit chip, characterized in that it comprises a leadframe formed from spaced-apart electrical connection leads (5), the integrated-chip being fixed to or supported by a front surface of the leads, electrical connection means (16) for connecting the integrated-chip to the electrical connection leads and a block (20) of an encapsulation material in which at least the electrical connection leads are at least partly embedded.
Claims22
A semiconductor package containing an integrated-circuit chip, the semiconductor package comprising:
- a leadframe formed from spaced apart electrical connection leads, each electrical connection lead having a rear face;
- an integrated-chip fixed to a front surface of the electrical connection leads;
- electrical connection means for connecting the integrated-chip to the electrical connection leads;
- and
- a block of an encapsulation material into which at least a portion of the electrical connection leads are embedded, the block having a rear face, wherein the rear face of the electrical connection leads and the rear face of the block form a rear face of the semiconductor package, and wherein the electrical connection leads have rear recesses covered by the encapsulation material.
A semiconductor package containing an integrated-circuit chip, the semiconductor package comprising:
- a leadframe formed from spaced apart electrical connection leads;
- an integrated-chip fixed to a front surface of the electrical connection leads;
- electrical connection means for connecting the integrated-chip to the electrical connection leads;
- and
- a block of an encapsulation material into which at least a portion of each of the electrical connection leads is embedded, wherein the electrical connection leads have one or more rear recesses covered by the encapsulation material.
A semiconductor package containing an integrated-circuit chip, the semiconductor package comprising:
- a leadframe formed from spaced apart electrical connection leads;
- an integrated-chip fixed to a front surface of the electrical connection leads;
- electrical connection means for connecting the integrated-chip to the electrical connection leads;
- and
- an encapsulation block into which at least a portion of each of the electrical connection leads are embedded, wherein the encapsulation block further comprises a forward projecting peripheral wall forming an annular wall.
A semiconductor package containing an integrated-circuit chip, the semiconductor package comprising:
- a leadframe formed from spaced apart electrical connection leads;
- an integrated-chip fixed to a front surface of the electrical connection leads;
- electrical connection means for connecting the integrated-chip to the electrical connection leads;
- and
- an encapsulation block into which at least a portion of each of the electrical connection leads is embedded, wherein the encapsulation block further comprises:
- a forward projecting peripheral wall forming an annular wall that extends a distance from the plate, and
- a ring of a filling material that fills a space that separates a periphery of the plate from the annular wall.
A semiconductor package containing an integrated-circuit chip, the semiconductor package comprising:
- a leadframe formed from spaced apart electrical connection leads;
- an integrated-chip fixed to a front surface of the electrical connection leads;
- electrical connection means for connecting the integrated-chip to the electrical connection leads;
- a block of an encapsulation material into which at least a portion of each of the electrical connection leads is embedded;
- a wall formed by the electrical connection leads and at least partly the block of encapsulation material;
- and
- one or more front electrical connection surfaces for connecting the integrated-chip, wherein the front electrical connection surfaces are not covered by the encapsulation material;
- wherein the encapsulation material fills one or more spaces formed between:
- the electrical connection leads with rear external electrical connection leads surfaces not covered by the encapsulation material, and
- the electrical connection leads with rear external electrical connection leads surfaces covered by the encapsulation material.
A semiconductor package containing an integrated-circuit chip, the semiconductor package comprising:
- a leadframe formed from spaced apart electrical connection leads, each electrical connection lead having a front face, an internal end part and an external end part;
- an integrated-chip fixed to a front surface of the electrical connection leads, the integrated-chip having a rear face fixed, via adhesive film, onto the front face of the internal end part of each electrical connection lead;
- electrical connection wires connect front pads of the integrated-chip to the front faces of the external end parts of the electrical connection leads;
- and
- a block of an encapsulation material into which at least a portion of the electrical connection leads is embedded.
Dependencies are inferred from the claim text.