Using chip lamination to couple an integrated circuit with a microstrip transmission line

A method for operatively coupling an integrated circuit with a microstrip transmission line through chip lamination, comprising:

• receiving a first semiconductor die containing the integrated circuit;
• and
• receiving a second semiconductor die containing the microstrip transmission line, wherein, unlike metal lines in the integrated circuit that have relatively small cross-sections, the microstrip transmission line has a cross-section that is large enough so that signal propagation is governed by inductance and capacitance (LC) instead of resistance and capacitance (RC);
• and
• laminating the first semiconductor die and the second semiconductor die together so that the integrated circuit on the first semiconductor die is operatively coupled with the microstrip transmission line in the second semiconductor die.

A computer system including an integrated circuit that is operatively coupled with a microstrip transmission line through chip lamination, comprising:

• the integrated circuit;
• a processor within the integrated circuit;
• a memory;
• a first semiconductor die containing the integrated circuit;
• and
• a second semiconductor die containing the microstrip transmission line, wherein, unlike metal lines in the integrated circuit that have relatively small cross-sections, the microstrip transmission line has a cross-section that is large enough so that signal propagation is governed by inductance and capacitance (LC) instead of resistance and capacitance (RC);
• wherein the first semiconductor die and the second semiconductor die are laminated together so that the integrated circuit on the first semiconductor die is operatively coupled with the microstrip transmission line in the second semiconductor die.