Intermediate structure for making integrated circuit device and wafer
AssigneeUnited Microelectronics Corp.
InventorMin-Chih John Hsuan
Life of this patent
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Abstract
A semiconductor die and an associated low resistance interconnect located primarily on the bottom surface of such die is disclosed. This arrangement provides a flexible packaging structure permitting easy interconnected with other integrated circuits; in this manner, a number of such circuits can be stacked to create high circuit density multi-chip modules. A process for making the device is further disclosed. To preserve structural integrity of a wafer containing such die during manufacturing, a through-hole via formed as part of the interconnect is filled with an inert material during operations associated with subsequent active device formation on such die.
Claims12
A semiconductor wafer including an integrated chip scale package to be used for integrated circuits, the wafer comprising:
- a top surface and a bottom surface;
- and
- wherein the semiconductor wafer is an unprocessed wafer having no active circuit layers or interconnect layers present on said top surface or said bottom surface of the semiconductor wafer;
- a plurality of vias formed in the unprocessed semiconductor wafer, each via having a via top portion beginning at said top surface of the unprocessed semiconductor wafer and extending through to a via bottom portion on said bottom surface of the unprocessed semiconductor wafer;
- wherein at least some of said plurality of vias include an input/output (I/O) interconnect structure physically and electrically coupled to said via bottom portion, and said I/O interconnect structure is located within an area on the bottom surface of the unprocessed wafer;
- and
- wherein the I/O interconnect structure is adapted such that an active circuit which is fabricated on the unprocessed semiconductor wafer as part of an integrated circuit at a later time than the I/O interconnect structure can be electrically connected to another integrated circuit without requiring further packaging operations to form pads or bumps for connecting I/O signals of such active circuit to such another integrated circuit.
Dependencies are inferred from the claim text.