US 7,030,459 B2 · Three-dimensional memory structure and manufacturing method thereof

Abstract

A three-dimensional memory structure and manufacturing method thereof is provided. A first stack layer is formed over a substrate. The first stack layer includes, from the substrate upwards, an n-type polysilicon layer, a conductive layer, an anti-fuse and another n-type polysilicon layer. The first stack layer is patterned to form a first stack circuit. Thereafter, a second stack layer is formed over the first stack circuit. The second stack layer includes, from the first stack circuit upwards, a p-type polysilicon layer, a conductive layer, an anti-fuse and another p-type polysilicon. The second stack layer is patterned to form a second stack circuit that crosses over the first stack circuit perpendicularly. The aforementioned steps are repeated to form more stack circuits above the substrate and hence produce a three-dimensional structure.

Claims17

Dependent claims

A three-dimensional memory structure, comprising:

a first stack line, having:
a first first-type polysilicon layer;
a second first-type polysilicon layer;
a first conductive layer between the first first-type polysilicon layer and the second first-type polysilicon layer;
and
a first anti-fuse between the first first-type polysilicon layer and the second first-type polysilicon layer;
and
a second stack line crossing over the first stacked line, having:
a first second-type polysilicon layer;
a second second-type polysilicon layer;
a second conductive layer between the first second-type polysilicon layer and the second second-type polysilicon layer;
and
a second anti-fuse between the first second-type polysilicon layer and the second second-type polysilicon layer, wherein each layer of the second stack line crosses over each layer of the first stack line.

10 more elements

A three-dimensional memory structure, comprising:

a plurality of first stack lines, wherein each first stacked line comprises:
a first upper first-type polysilicon layer;
a first lower first-type polysilicon layer;
a first conductive layer between the upper and the lower first-type polysilicon layers;
and
a first anti-fuse between the first upper first-type polysilicon layer and the first lower first-type polysilicon layer;
a first dielectric layer in a space between the first stack lines;
a plurality of second stack lines crossing over the plurality of the first stack lines, wherein a pattern of the upper first-type polysilicon layer is substantially conformal to a shape of an intersection between each second stacked line and each first stacked line, wherein each second stack line comprises:
an upper second-type polysilicon layer;
a lower second-type polysilicon layer;
a second conductive layer between the upper and the lower second-type polysilicon layers;
and
a second anti-fuse between the upper and the lower second-type polysilicon layers;
a second dielectric layer in a space between the second stacked lines;
a plurality of third stacked lines crossing over the plurality of the second stacked lines, wherein a pattern of the upper second-type polysilicon layer is substantially conformal to a shape of an interaction between each third stack line and each first stack line, and wherein each third stack line comprises:
a second upper first-type polysilicon layer;
a second lower first-type polysilicon layer;
a third conductive layer between the second upper and the second lower first-type polysilicon layers;
and
a third anti-fuse between the second upper first-type polysilicon layer and the second lower first-type polysilicon layer;
a third dielectric layer in a space between the third stacked lines;
and
at least a plug in the second dielectric layer connecting the first conductive layer and the second lower first-type polysilicon layer.

20 more elements

Dependencies are inferred from the claim text.

Three-dimensional memory structure and manufacturing method thereof

Life of this patent

Three-dimensional memory structure and manufacturing method thereof

Life of this patent

Abstract

Claims17