Low voltage transient voltage suppressor
AssigneeSemiconductor Components Industries, LLC
InventorsFrancine Y. Robb, Jeffrey Pearse, David M. Heminger, Stephen P. Robb
Life of this patent
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Abstract
A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.
Claims16
A semiconductor device for suppressing an external transient voltage, comprising an insulated gate bipolar transistor (IGBT) having a gate terminal and a first conduction terminal coupled to receive the external transient voltage, first and second diodes coupled in a back to back fashion between the gate and first conduction terminals, and a second conduction terminal to shunt a surge current flowing through the first conduction terminal in response to the external transient voltage exceeding a predetermined level.
A semiconductor device for suppressing an external transient voltage, comprising an insulated gate bipolar transistor (IGBT) having a gate terminal and a first conduction terminal coupled to receive the external transient voltage and a second conduction terminal to shunt a surge current flowing through the first conduction terminal in response to the external transient voltage exceeding a predetermined level, wherein the semiconductor device further includes:
- a semiconductor substrate having a top surface for forming the first conduction terminal and the gate terminal of the IGBT and a bottom surface;
- a body region of a first conductivity type formed in the semiconductor substrate for inverting to form a channel of the IGBT;
- an emitter region formed at the top surface for receiving the surge current from the first conduction terminal;
- a drift region having a second conductivity type and coupled to the channel for conducting the surge current;
- a collector region of the first conductivity type formed adjacent to the drift region for routing the surge current between the drift region and the second conduction terminal;
- and
- a semiconductor package having a die flag for mounting the semiconductor substrate, wherein the collector region is electrically coupled to the die flag for routing the surge current to an external node.
Dependencies are inferred from the claim text.