US 7,030,445 B2Granted

Power MOSFET, power MOSFET packaged device, and method of manufacturing power MOSFET

AssigneeRenesas Technology Corp.

InventorKazuya Fukuhara

Life of this patent

Estimating the term…

Loading patent…

Abstract

A source terminal layer, a gate terminal layer, and a drain terminal layer are disposed on main surfaces, opposite to each other, on main surfaces of a semiconductor substrate. These terminal layers are laid out on the respective main surfaces with such sizes as to fall within the areas of the respective main surfaces and joined to their corresponding source, gate, and drain electrodes. A power MOSFET is packaged on a circuit board such that the respective main surfaces intersect substantially at right angles to the circuit board. By a terminal board isolating step or a method of evaporating a metal layer onto the source, gate, and drain electrodes, the power MOSFET is formed with the source terminal layer, gate terminal layer, and drain terminal layer at the stage of a semiconductor wafer.

Claims3

Dependent claims

A power MOSFET packaged device comprising:

a power MOSFET comprising:
a semiconductor substrate having a first surface and a second surface opposite to each other, the semiconductor substrate having a source electrode and a gate electrode provided on the first surface and a drain electrode provided on the second surface;
a source terminal layer disposed on the first surface and joined to the source electrode;
a gate terminal layer disposed on the first surface and joined to the gate electrode;
and a drain terminal layer disposed on the second surface and joined to the drain electrode;
wherein the source terminal layer and the gate terminal layer are respectively disposed on the first surface with such sizes as to fall within the area of the first surface, and the drain terminal layer is disposed with such a size as to fall within the area of the second surface, and a circuit board, wherein the power MOSFET is packaged in such a manner that the respective first and second surfaces of the semiconductor substrate in the power MOSFET are substantially normal to the circuit board.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/849,035Filed 20 May 2004
Priority: JP 2003-14216520 May 2003
Published: US 2005/0012117 A120 Jan 2005
Granted: 18 Apr 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10W 72/013
Manufacture or treatment: of die-attach connectors
H10D 84/83
Of only field-effect components: of only insulated-gate FETs [IGFET]
H10W 72/30
Interconnections or connectors in packages: die-attach connectors
H05K 3/3442
Leadless components: having edge contacts, e.g. leadless chip capacitors, chip carriers