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US 7,030,317 B1Granted
Electronic assembly with stacked integrated circuit die
AssigneeDelphi Technologies, Inc.
InventorTodd P. Oman
Life of this patent
Estimating the term…
Abstract
An electronic assembly with a plurality of stacked integrated circuit (IC) die includes a base substrate, a first IC die, a second IC die, a signal routing first interconnect and a signal routing second interconnect. The first interconnect is partially positioned between the first and second IC dies. The second interconnect is partially positioned adjacent the first side of the second IC die. The first interconnect couples a first contact of the first IC die to a first trace of the base substrate and a second contact of the second IC die to a second trace of the base substrate. The first and second interconnects, in combination, couple the first contact of the second IC die to the first trace.
Claims19
An electronic assembly with stacked integrated circuit (IC) die, comprising:
- a base substrate including an electrically conductive first trace and an electrically conductive second trace formed on a first surface of the base substrate;
- a first IC die having a first side and a second side opposite the first side, wherein the first side of the first IC die includes an electrically conductive first contact and the second side of the first IC die includes an electrically conductive second contact, and wherein the second contact of the first IC die is coupled to the second trace;
- a second IC die having a first side and a second side opposite the first side, wherein the first side of the second IC die includes another electrically conductive first contact and the second side of the second IC die includes another electrically conductive second contact;
- a signal routing first interconnect partially positioned between the first and second IC dies;
- and
- a signal routing second interconnect partially positioned adjacent the first side of the second IC die, wherein the first interconnect couples the first contact of the first IC die to the first trace and the second contact of the second IC die to the second trace, and wherein the first and second interconnects in combination couple the first contact of the second IC die to the first trace.
3 more elements
An electronic assembly with stacked integrated circuit (IC) die, comprising:
- a base substrate including an electrically conductive first trace, an electrically conductive second trace and an electrically conductive third trace formed on a first surface of the base substrate;
- a first IC die having a first side and a second side opposite the first side, wherein the first side of the first IC die includes an electrically conductive first contact and the second side of the first IC die includes an electrically conductive second contact and an electrically conductive third contact, and wherein the second contact of the first IC die is coupled to the second trace and the third contact of the first IC die is coupled to the third trace;
- a second IC die having a first side and a second side opposite the first side, wherein the first side of the second IC die includes another electrically conductive first contact and the second side of the second IC die includes another electrically conductive second contact and another electrically conductive third contact;
- a signal routing first interconnect partially positioned between the first and second IC dies;
- and
- a signal routing second interconnect partially positioned adjacent the first side of the second IC die, wherein the first interconnect couples the first contact of the first IC die to the first trace, the second contact of the second IC die to the second trace and the third contact of the second IC die to the third trace, and wherein the first and second interconnects in combination couple the first contact of the second IC die to the first trace.
3 more elements
An electronic assembly with stacked integrated circuit (IC) die, comprising:
- a base substrate including an electrically conductive first trace, an electrically conductive second trace and an electrically conductive third trace formed on a first surface of the base substrate;
- a first IC die having a first side and a second side opposite the first side, wherein the first side of the first IC die includes an electrically conductive first contact and the second side of the first IC die includes an electrically conductive second contact and an electrically conductive third contact, and wherein the second contact of the first IC die is coupled to the second trace and the third contact of the first IC die is coupled to the third trace;
- a second IC die having a first side and a second side opposite the first side, wherein the first side of the second IC die includes another electrically conductive first contact and the second side of the second IC die includes another electrically conductive second contact and another electrically conductive third contact;
- a signal routing first interconnect partially positioned between the first and second IC dies;
- a signal routing second interconnect partially positioned adjacent the first side of the second IC die, wherein the first interconnect couples the first contact of the first IC die to the first trace, the second contact of the second IC die to the second trace and the third contact of the second IC die to the third trace, and wherein the first and second interconnects in combination couple the first contact of the second IC die to the first trace;
- and
- a case providing an enclosure for the base substrate, the first and second IC dies and the first and second interconnects.
4 more elements
Dependencies are inferred from the claim text.