Method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and mask-pattern generation method

A method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and including a first wiring layer which is not the uppermost layer among said plurality of wiring layers and a second wiring layer higher than said first wiring layer in said plurality of wiring layers, comprising:

• (a) a step of depositing a first insulating film, a second insulating film, and a third insulating film in order on said first wiring layer;
• (b) a step of patterning a first mask film having an opening in an area in which holes will be formed on said third insulating film and etching said third insulating film under presence of said first mask film;
• (c) a step of removing said first mask film and depositing a fourth insulating film and a fifth insulating film in order on said third and second insulating films;
• (d) a step of patterning a second mask film having an opening in an area in which trenches will be formed on said fifth insulating film and etching said fifth insulating film under presence of said second mask film;
• (e) a step of etching said fourth insulating film by using the second mask film or said fifth insulating film as a mask, forming the trenches patterned on said fifth insulating film on said fourth insulating film, etching said second insulating film by using said third insulating film as a mask, and forming the holes patterned on said insulating film on said second insulating film;
• (f) a step of patterning a third mask film for covering at least some of said holes;
• (g) a step of etching said first insulating film at bottoms of said holes and said third insulating film at bottoms of said trenches under presence of the third mask film and patterned fifth insulating film;
• (h) a step of removing said third mask film and forming a conductive film for filling up said trenches and holes;
• and
• (i) a step of removing said conductive film from areas other than said trenches and forming wirings for comprising said second wiring layer and a conductive member.

A method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and including a first wiring layer which is not the uppermost layer among said plurality of wiring layers and a second wiring layer higher than said first wiring layer in said plurality of wiring layers, comprising:

• (a) a step of depositing a first insulating film, a second insulating film, a third insulating film, a fourth insulating film, and a fifth insulating film in order on said first wiring layer;
• (b) a step of pattering a first mask film having an opening in an area in which holes will be formed on said fifth insulating film, etching said fifth, fourth, third, and second insulating films under presence of said first mask film, and forming holes;
• (c) a step of removing said first mask film, forming a second mask film on said fifth insulating film, exposing an area in which trenches will be formed, developing said second mask film, and leaving said mask film in areas other than the area in which said trenches will be formed and in said holes;
• (d) a step of etching said fifth and the fourth insulating film and forming trenches presence of the second mask film;
• (e) a step of removing said second mask film and patterning a third mask film for covering at least some of said holes;
• (f) a step of etching said first insulating film at the bottoms of said holes under presence of said third mask film;
• (g) a step of removing said third mask film and forming a conductive film for filling up said trenches and holes;
• and
• (h) a step of removing said conductive film in areas other than said trenches and forming wiring comprising said second wiring layer and a conductive member.

A method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and including a first wiring layer which is not the uppermost layer among said plurality of wiring layers and a second wiring layer higher than said first wiring layer in said plurality of wiring layers, comprising:

• (a) a step of depositing a seventh insulating film for covering said first wiring layer;
• (b) a step of patterning a first mask film having an opening in an area in which holes will be formed on said seventh insulating film, etching said seventh insulating film under presence of said first mask film, and removing said seventh insulating film onto wirings comprising said first wiring layer;
• (c) a step of depositing a sixth insulating film on the entire surface of a semiconductor substrate including insides of said holes;
• (d) a step of pattering a third mask film for covering at least some of said holes;
• (e) a step of etching said sixth insulating film under presence of said third mask film;
• (f) a step of removing said third mask film and forming a conductive film for filling up said holes;
• (g) a step of removing said conductive film from areas other than said holes and forming a conductive member to be connected to wirings comprising said second wiring layer;
• and
• (h) a step of depositing a second conductive film on the entire surface of said semiconductor substrate, pattering said second conductive film, and forming said second wiring layer.

A method of generating a mask-pattern used for a method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and including a first wiring layer which is not the uppermost layer among said plurality of wiring layers and a second wiring layer higher than said first wiring layer in said plurality of wiring layers, comprising:

• (a) a first step of determining an intersectional area where a first power-source wiring to which a first potential is assigned among power-source wiring comprising said wiring layer intersects a second power-source wiring to which a second potential different from said first potential is assigned among power-source wiring comprising said second wiring layer;
• a second step of generating a hole pattern in said intersectional area;
• and
• a third step of expanding the width of said hole pattern so as not to reach wiring areas of said first and second wiring layers adjacent to said hole pattern.