Dual-gate structure and method of fabricating integrated circuits having dual-gate structures

A method of manufacturing an integrated circuit device, comprising the following steps:

• forming a first high-K dielectric layer in a first area defined for a first gate structure of a first device and in a second area defined for a second gate structure of a second device;
• processing said first high-K dielectric layer to lower an etch rate to an etchant of said first high-K dielectric layer;
• forming a second high-K dielectric layer in said first and second areas over said first high-K dielectric layer, said first high-K dielectric layer having a lower etch rate to said etchant relative to said second high-K dielectric layer;
• etching said second high-K dielectric layer from said second area to said first high-K dielectric layer.

A method of fabricating a dual-gate structure on a substrate, comprising the following steps:

• forming a first dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure;
• forming a second dielectric layer in said first and second areas, said first dielectric layer having a lower etch rate to an etchant relative to said second dielectric layer;
• etching said second dielectric layer from said second area to said first dielectric layer wit said etchant;
• and
• forming a gate conductive layer in said first and second areas over said second dielectric layer and first dielectric layer, respectively,
• wherein said first dielectric layer is a high-K dielectric layer and said second dielectric layer is a non high-K dielectric layer, and
• wherein said first and second areas comprise channel areas having the same conductivity.

A method of fabricating a dual-gate structure on a substrate, comprising the following steps:

• forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure;
• forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer;
• forming an interfacial layer between said substrate and said first high-K dielectric layer in said first and second areas;
• etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant;
• and
• forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively.

A method of fabricating a dual-gate structure on a substrate, comprising the following steps:

• forming a first high-K dielectric layer in a first area defined for a first gate structure and in a second area defined for a second gate structure;
• forming a second high-K dielectric layer in said first and second areas, said first high-K dielectric layer having a lower etch rate to an etchant relative to said second high-K dielectric layer;
• etching said second high-K dielectric layer from said second area to said first high-K dielectric layer with said etchant;
• annealing a remaining portion of said second high-K dielectric layer and said first high-K dielectric layer after said etching step;
• and
• forming a gate conductive layer in said first and second areas over said second high-K dielectric layer and first high-K dielectric layer, respectively.