Method for simultaneous degas and baking in copper damascene process

A method for forming copper damascene features in low-K porous dielectric layers with improved electrical properties including reducing moisture and etching residues from a damascene opening comprising the steps of:

• providing a semiconductor process wafer comprising at least one damascene opening formed to extend through a thickness of at least one inorganic low-K dielectric layer, said opening comprising one of a single damascene opening and a dual damascene opening;
• etching through an etch stop layer at the damascene opening bottom portion to expose an underlying copper area;
• then carrying out in-situ a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient;
• then carrying out an in-situ sputter-clean process comprising hydrogen gas;
• and,
• then forming a barrier layer in-situ to line the damascene opening.