Method for forming contact hole and spacer of semiconductor device
AssigneeHynix Semiconductor Inc.
InventorsSung-Chan Park, Phil-Goo Kong, Kuk-Han Yoon
Life of this patent
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Abstract
Disclosed is a contact hole forming method capable of reducing parasitic capacitance between a conductive layer patterns, preventing bad contacts caused by mask misalignment and effectively filling an interlayer insulating layer between the conductive layer patterns. The method including forming many conductive layer patterns on a substrate, forming an interlayer insulating layer on a resulting structure where the conductive layer patterns are completed, exposing a conductive layer pattern which at least one sidewall of a contact region between conductive layer patterns is neighboring the contact region, and forming an insulating spacer on the sidewall of the exposed conductive layer pattern.
Claims9
A method for forming contact openings between bit line patterns, the method comprising the steps of:
- a) forming bit line patterns over a substrate;
- b) forming an interlayer insulating layer over the substrate and the bit line patterns;
- c) etching the interlayer insulating layer by using the bit line patterns and an etching mask defining a straight line shape as a mask, thereby forming at least one straight line shaped self-aligned contact opening between neighboring bit line patterns;
- and
- d) forming spacers on sidewalls of the bit line patterns only exposed through the contact opening.
Dependencies are inferred from the claim text.