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US 7,029,983 B2Granted
Methods of forming MIM type capacitors by forming upper and lower electrode layers in a recess that exposes a source/drain region of a transistor and MIM capacitors so formed
AssigneeSamsung Electronics Co., Ltd.
InventorHong-Ki Kim
Life of this patent
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Abstract
A MIM capacitor can be formed by forming an insulating layer on a source/drain region of a transistor. A first pattern is formed on the insulating layer. A recess is formed in the insulating layer using the first pattern, wherein the recess exposes the source/drain region. A first electrode layer is formed in the recess on the source/drain region. A dielectric layer and a second electrode layer are formed on the first electrode layer in the recess. A second pattern is formed on the second electrode layer. The MIM capacitor is formed by removing a portion of the second electrode and the dielectric layer using the second pattern.
Claims22
A capacitor of a semiconductor device, comprising:
- an interlayer dielectric layer pattern disposed on a semiconductor substrate, the interlayer dielectric layer having an opening exposing a top surface of the semiconductor substrate;
- a first lower electrode extending along a sidewall of the opening to a level below a top surface of the interlayer dielectric pattern and covering a top surface of the semiconductor substrate which is exposed through the opening;
- a second lower conductive layer pattern covering an inner wall of the first lower electrode, the second lower conductive layer pattern extending along the sidewall to a level higher than the level of the first lower electrode;
- a dielectric layer pattern covering the exposed surfaces of the first lower electrode and the second lower conductive layer pattern;
- and
- an upper electrode disposed on the dielectric layer pattern.
3 more elements
A method of forming a Metal-Insulator-Metal (MIM) capacitor comprising:
- forming an insulating layer pattern on a source/drain region of a transistor;
- forming a recess in the insulating layer pattern that exposes the source/drain region;
- forming a first electrode layer in the recess, including forming a first layer of the first electrode layer directly on the source/drain region and extending along sidewalls of the recess and forming a second layer of the first electrode layer on the first layer;
- forming a dielectric layer and a second electrode layer on the first electrode layer in the recess;
- and
- forming a MIM capacitor by removing a portion of the second electrode layer and the dielectric layer;
- and
- wherein forming a first electrode layer comprises:
- forming the first layer of the first electrode layer on the side wall of the recess and outside the recess on a surface of the insulating layer;
- forming the second layer of the first electrode layer extending along the side wall of the recess with the first layer of the first electrode layer therebetween;
- etching the first layer of the first electrode layer from the surface of the insulating layer and from the side wall into the recess beyond an opening of the recess to provide an exposed portion of the side wall;
- and
- avoiding etching the second layer of the first electrode layer from the side wall into the recess beyond the opening to form a gap between the side wall and the second layer of the first electrode layer.
10 more elements
A method of forming a Metal-Insulator-Metal (MIM) capacitor comprising:
- forming an insulating layer pattern on a source/drain region of a transistor;
- forming a recess in the insulating layer pattern that exposes the source/drain region;
- forming a first electrode layer in the recess;
- forming a dielectric layer and a second electrode layer on the first electrode layer in the recess;
- and
- forming a MIM capacitor by removing a portion of the second electrode layer and the dielectric layer using the second pattern;
- and
- wherein forming a first electrode layer comprises:
- forming a first layer of the first electrode layer on a side wall of the recess and outside the recess on a surface of the insulating layer;
- and
- forming a second layer of the first electrode layer on the first layer of the first electrode layer;
- and
- wherein the method further comprises:
- etching the insulating layer to reduce a height thereof;
- and
- avoiding etching the second layer of the first electrode layer so that the second layer of the first electrode layer protrudes from the recess beyond the reduced height surface of the insulating layer.
13 more elements
A method of forming a Metal-Insulator-Metal (MIM) capacitor comprising:
- forming an insulating layer pattern on a source/drain region of a transistor;
- forming a recess in the insulating layer pattern that exposes the source/drain region;
- forming a first electrode layer in the recess;
- forming a dielectric layer and a second electrode layer on the first electrode layer in the recess;
- and
- forming a MIM capacitor by removing a portion of the second electrode layer and the dielectric layer using the second pattern;
- and
- wherein forming a first electrode layer comprises:
- forming a first layer of the first electrode layer on a side wall of the recess and outside the recess on a surface of the insulating layer;
- and
- forming a second layer of the first electrode layer on the first layer of the first electrode layer;
- and
- wherein the method further comprises:
- avoiding etching the second layer of the first electrode layer from the side wall into the recess beyond the opening to form a gap between the side wall and the second layer of the first electrode layer, including etching the first electrode layer using an isotropic etch process with an etchant having an etch selectivity with respect to the second layer of the first electrode layer.
11 more elements
A method of forming a Metal-Insulator-Metal (MIM) capacitor comprising:
- forming an insulating layer having a recess therein that exposes an underlying source/drain region of a transistor;
- forming a first lower electrode layer of a MIM capacitor in the recess directly on the source/drain region and extending along a side wall of the recess;
- forming a second lower electrode layer of the MIM capacitor in the recess on the first lower electrode layer;
- and
- forming a dielectric layer and an upper electrode layer of the MIM capacitor on the second lower electrode layer in the recess to provide the MIM capacitor;
- and
- wherein forming the first lower electrode layer comprises:
- forming the first lower electrode layer extending along the side wall of the recess and outside the recess on a surface of the insulating layer;
- and
- etching the first lower electrode layer from the surface of the insulating layer and from the side wall into the recess beyond an opening of the recess to provide an exposed portion of the side wall;
- and
- avoiding etching the second lower electrode layer from the side wall into the recess beyond the opening to form a gap between the side wall and the second lower electrode layer.
9 more elements
A method of fabricating a capacitor of a semiconductor device comprising:
- forming an interlayer dielectric layer pattern on the semiconductor substrate, the interlayer dielectric layer having an opening exposing a semiconductor substrate;
- sequentially stacking a first lower conductive layer, a second lower conductive layer, and a sacrificial layer on an entire surface of the semiconductor substrate including the interlayer dielectric layer pattern;
- successively etching the sacrificial layer until a top surface of the interlayer dielectric layer pattern is exposed, to form a first lower conductive layer pattern, a second lower conductive layer pattern, and a sacrificial layer pattern, which sequentially fill an inner wall of the opening;
- removing the sacrificial layer pattern;
- etching the first lower conductive layer pattern using an etch recipe having an etch selectivity with respect to the second lower electrode pattern to form a first lower electrode having a lower top surface than that of the interlayer dielectric layer pattern;
- and
- sequentially forming a dielectric layer and an upper electrode layer on an entire surface of the semiconductor substrate including the first lower electrode.
4 more elements
A method of fabricating a capacitor of a semiconductor device comprising:
- forming an interlayer dielectric layer pattern on the semiconductor substrate, the interlayer dielectric layer having an opening exposing a semiconductor substrate;
- sequentially stacking a first lower conductive layer, a second lower conductive layer, and a sacrificial layer on an entire surface of the semiconductor substrate including the interlayer dielectric layer pattern;
- successively etching the sacrificial layer until a top surface of the interlayer dielectric layer pattern is exposed, to form a first lower conductive layer pattern, a second lower conductive layer pattern, and a sacrificial layer pattern, which sequentially fill an inner wall of the opening;
- removing the sacrificial layer pattern;
- etching the first lower conductive layer pattern to form a first lower electrode having a lower top surface than that of the interlayer dielectric layer pattern;
- sequentially forming a dielectric layer and an upper electrode layer on an entire surface of the semiconductor substrate including the first lower electrode;
- and
- wherein forming the first lower electrode uses a mixed solution of CH3COOH, CH3COONH4, NH4F, and a deionized water.
5 more elements
A method of fabricating a capacitor of a semiconductor device comprising:
- forming an interlayer dielectric layer pattern on the semiconductor substrate, the interlayer dielectric layer having an opening exposing a semiconductor substrate;
- sequentially stacking a first lower conductive layer, a second lower conductive layer, and a sacrificial layer on an entire surface of the semiconductor substrate including the interlayer dielectric layer pattern;
- successively etching the sacrificial layer until a top surface of the interlayer dielectric layer pattern is exposed, to form a first lower conductive layer pattern, a second lower conductive layer pattern, and a sacrificial layer pattern, which sequentially fill an inner wall of the opening;
- removing the sacrificial layer pattern;
- etching the first lower conductive layer pattern to form a first lower electrode having a lower top surface than that of the interlayer dielectric layer pattern;
- sequentially forming a dielectric layer and an upper electrode layer on an entire surface of the semiconductor substrate including the first lower electrode;
- and
- wherein removing the sacrificial layer pattern is followed by forming the first lower electrode.
5 more elements
Dependencies are inferred from the claim text.