Method of forming a PIP capacitor

A method of forming a polysilicon-insulator-polysilicon (PIP) capacitor, the method comprising:

• providing a workpiece, the workpiece including at least one capacitor region and at least one transistor region;
• forming a first oxide layer over the workpiece;
• depositing a first polysilicon layer over the first oxide layer;
• forming a mask layer over the first polysilicon layer, the mask layer comprising a pattern for at least one bottom electrode in the at least one capacitor region and a pattern for at least one floating gate in the at least one transistor region;
• forming a first poly-oxide region over the pattern for each at least one floating gate and forming a second poly-oxide region over the pattern for each at least one bottom electrode, the first poly-oxide region having a first top surface and the second poly-oxide region having a second top surface;
• removing the mask layer, leaving portions of the first polysilicon layer exposed;
• using the first poly-oxide region and the second poly-oxide region as a mask to remove the exposed portions of the first polysilicon layer and form at least one floating gate in the at least one transistor region and the at least one bottom electrode in the at least one capacitor region, the at least one floating gate having first sidewalls and the at least one bottom electrode having second sidewalls;
• forming a second oxide layer over the top surface of the first poly-oxide region, the second top surface of the second poly-oxide region, the second sidewalls of the at least one bottom electrode, the first sidewalls of the at least one floating gate, and the first oxide layer;
• depositing a second nitride layer over the second oxide layer;
• removing a portion of the second nitride layer to expose at least a portion of the second poly-oxide region over the bottom electrode in the capacitor region;
• removing the second oxide layer and the second poly-oxide region from over a top surface of the bottom electrode in the at least one capacitor region;
• removing at least portions of the second nitride layer, leaving a spacer comprising the second nitride layer on the sidewalls of the at least one floating gate;
• forming a third oxide layer over at least the at least one capacitor bottom electrode in the capacitor region;
• depositing a second polysilicon layer over the third oxide layer;
• depositing a second photoresist layer over the second polysilicon layer;
• patterning the second photoresist layer;
• and
• using the second photoresist layer to pattern the second polysilicon layer, forming a control gate proximate each at least one floating gate in the at least one transistor region, and forming a top electrode over each bottom electrode in the at least one capacitor region, wherein the bottom electrode, the top electrode, and the third oxide layer disposed between the bottom electrode and top electrode comprise a PIP capacitor.