Silicide method for CMOS integrated circuits

A method of eliminating metal silicide spikes in integrated circuits, comprising:

• forming a first gate structure over a p-well region and a second gate structure over a n-well region wherein said n-well region and said p-well region are formed in a semiconductor substrate;
• forming first sidewall structures adjacent said first gate structure and second sidewall structures adjacent said second gate structure;
• forming source and drain regions in said p-well region adjacent said first sidewall structure and in said n-well region adjacent said second sidewall structure;
• forming germanium implanted regions said source and drain regions;
• annealing said germanium implanted regions and said source and drain regions with a rapid thermal anneal at temperatures exceeding 1000° C.;
• forming a nickel metal layer over said source and drain regions;
• and
• annealing said metal layer to form nickel silicide regions over said source and drain regions.

A method of forming metal silicide regions in source and drain regions in integrated circuits, comprising:

• forming a first gate structure over a p-well region and a second gate structure over a n-well region wherein said n-well region and said p-wall region are formed in a semiconductor substrate;
• forming first sidewall structures adjacent said first gate structure and second sidewall structures adjacent said second gate structure;
• forming n-type source and drain regions in said p-well region adjacent said first sidewall structure and p-type source and drain regions in said n-well region adjacent said second sidewall structure;
• selectively forming germanium implanted regions in said n-type source and drain regions;
• annealing said germanium implanted regions and said source and drain regions with a rapid thermal anneal with temperatures exceeding 1000° C.;
• forming a nickel metal layer over said source and drain regions;
• and
• annealing said metal layer to form nickel silicide regions over said source and drain regions.

A method for selectively enhancing the formation of metal silicide regions in source and drain regions in integrated circuits, comprising:

• forming a first gate structure over a p-well region and a second gate structure over a n-well region wherein said n-well region and said p-well region are formed in a semiconductor substrate;
• forming first sidewall structures adjacent said first gate structure and second sidewall structures adjacent said second gate structure;
• forming n-type source and drain regions in said p-well region adjacent said first sidewall structure and p-type source and drain regions in said n-well region adjacent said second sidewall structure;
• selectively forming germanium implanted regions in said p-type source and drain regions;
• annealing said germanium implanted regions and said source and drain regions with a rapid thermal anneal at temperatures exceeding 1000° C.;
• forming a nickel metal layer over said source and drain regions;
• and
• annealing said metal layer to form nickel silicide regions over said source and drain regions.