Method for manufacturing semiconductor device and semiconductor device
AssigneeSeiko Epson Corporation
InventorAkihiro Murata
Life of this patent
Estimating the term…
Abstract
A method for manufacturing a semiconductor device includes the steps of forming a stress relief layer on a wafer such that the stress relief layer is away from at least part of electrodes formed on the wafer; forming a wiring layer in which lines that extend from the electrodes to the stress relief layer are formed; forming outer electrodes that are over the stress relief layer and are connected to the lines in the wiring layer; and forming a dielectric layer by applying dielectric liquid by an inkjet method to portions in the lines where the outer electrodes are connected to form a capacitor. The step of forming the dielectric layer is conducted after the step of forming the wiring layer.
Claims14
A method for manufacturing a semiconductor device, the method comprising the steps of:
- forming a stress relief layer on a wafer such that the stress relief layer is away from at least part of electrodes formed on the wafer;
- forming a wiring layer consisting of wiring extending over the stress relief layer;
- forming outer electrodes over predetermined portions of the wiring layer to electrically connect the outer electrodes to the wiring layer over the stress relief layer wherein the method further comprises the step of:
- forming a dielectric layer by applying dielectric liquid by an inkjet method on the predetermined portions after the step of forming the wiring layer, such that the wiring layer, the dielectric layer and the outer electrodes form capacitors above the stress relief layer.
A method for manufacturing a semiconductor device, the method comprising the steps of:
- forming a stress relief layer on a wafer such that the stress relief layer is away from at least part of electrodes formed on the wafer;
- forming a wiring layer consisting of wiring extending over the stress relief layer;
- forming outer electrodes over predetermined portions of the wiring layer to electrically connect the outer electrodes to the wiring layer over the stress relief layer;
- and
- forming on the stress relief layer an inductor, which is electrically connected to the wiring layer, by applying conductive liquid in a spiral pattern by an inkjet method, after the step of forming the wiring layer.
A method for manufacturing a semiconductor device, the method comprising the steps of:
- forming a stress relief layer on a wafer such that the stress relief layer is away from at least part of electrodes formed on the wafer;
- forming a wiring layer consisting of wiring extending over the stress relief layer from the electrodes;
- forming outer electrodes over predetermined portions of the wiring layer to electrically connect the outer electrodes to the wiring layer wherein the method further comprises the step of:
- forming multiple wiring layers in which stress relief layers and wiring layers are alternately laminated, adjacent wiring layers are electrically connected to each other,
- wherein the step of forming the multiple wiring layers includes the step of forming a filter having at least one capacitor that has a dielectric layer between the wiring layers at the portions where the adjacent wiring layers are electrically connected to each other or between the top wiring layer and the outer electrodes and at least one inductor that is at least one wiring layer formed in a spiral pattern in the multiple wiring layers, and
- wherein, in the step of forming the filter, applying dielectric liquid by an inkjet method forms the dielectric layer and applying conductive liquid in the spiral pattern by the inkjet method forms the inductor.
A method for manufacturing a semiconductor device, the method comprising the steps of:
- forming a stress relief layer on a wafer such that the stress relief layer is away from at least part of electrodes formed on the wafer;
- forming a wiring layer consisting of wiring extending over the stress relief layer;
- forming outer electrodes over predetermined portions of the wiring layer to electrically connect the outer electrodes to the wiring layer over the stress relief layer;
- and
- forming multiple wiring layers in which stress relief layers and wiring layers are alternately laminated, and adjacent wiring layers are electrically connected to each other,
- wherein, in the step of forming the multiple wiring layers, the wiring layer on one face of the top stress relief layer is formed to be a ground plane such that lines having a microstrip line structure are formed in the wiring layer on the other face of the top stress relief layer, and
- wherein the step of forming the multiple wiring layers includes the step of forming a plurality of strip lines that are electromagnetically coupled to each other and are spaced at predetermined intervals by applying conductive liquid by an inkjet method to the lines having the microstrip line structure to form a bandpass filter.
Dependencies are inferred from the claim text.