US 7,029,932 B1Granted

Circuit and method for measuring contact resistance

AssigneeTexas Instruments Incorporated

InventorsDaryl T. Hiser, Stephen J. Sanchez

Life of this patent

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Abstract

Parametric testing of an integrated circuit chip includes pressing first, second, and third contact elements (PRB-1,2,3) against first, second and third terminals (P1–3), respectively, of the integrated circuit and forcing first, second, and third reference currents (Iref) through first, second, and third circuit paths each including a corresponding ESD diode. Each path includes two of the contact elements, two associated contact resistances, and one of the ESD diodes. First, second, and third voltages (Vm1–3) are measured across the three circuit paths. Three equations representative of the three voltages are simultaneously solved to determine three contact resistances between the various contact elements and integrated circuit terminals. The voltages across the three contact resistances are computed by multiplying them by parametric test currents and are added to or subtracted from measured voltages of the contact elements to obtain accurate values of voltages of the integrated circuit terminals.

Claims18

Dependent claims

A method of testing an integrated circuit chip including a first terminal, a second terminal, and a third terminal, the method comprising:

(a) providing first, second, and third ESD diodes on the integrated circuit chip, anodes of the first and second ESD diodes being coupled to the second terminal, cathodes of the first and third ESD diodes being coupled to the first terminal, an anode of the third ESD diode and a cathode of the second ESD diode being coupled to the third terminal, the first, second, and third ESD diodes having known first, second and third forward resistances, respectively;
(b) pressing first, second, and third contact elements against the first, second and third terminals, respectively;
(c) forcing a first reference current through a first circuit path including the second contact element, the second ESD diode, the third contact resistance, and the third contact element and measuring a first voltage across the first circuit path,
forcing a second reference current through a second circuit path including the second contact element, the first ESD diode, and the first contact element and measuring a second voltage across the second circuit path, and
forcing a third reference current through a third circuit path including the third contact element, the third ESD diode, and the first contact element and measuring a third voltage across the third circuit path;
(d) solving three equations representative of the first, second, and third voltages to determine first, second, and third contact resistances between the first contact element and the first terminal, the second contact element and the second terminal, and the third contact element and the third terminal, respectively;
and
(e) performing a parametric test operation on the integrated circuit chip to determine a parameter dependent on a voltage of the third terminal by determining a first test current through the third contact resistance and using the first test current to determine a voltage drop across the third contact resistance, and computing a value equal to a measurement voltage of the third contact element offset by the amount of the voltage drop across the third contact resistance to obtain a more accurate measurement value representative of the voltage of the third terminal.

5 more elements

A system for testing an integrated circuit chip including a first terminal, a second terminal, and a third terminal, the system comprising:

(a) first, second, and third ESD diodes on the integrated circuit chip, anodes of the first and second ESD diodes being coupled to the second terminal, cathodes of the first and second ESD diodes being coupled to the first terminal, an anode of the third ESD diode and a cathode of the second ESD diode being coupled to the third terminal, the first, second, and third ESD diodes having known first, second and third forward resistances, respectively;
(b) means for pressing first, second, and third contact elements against the first, second and third terminals, respectively;
(c) means for forcing a first reference current through a first circuit path including the second contact element, the second ESD diode, the third contact resistance, and the third contact element and measuring a first voltage across the first circuit path,
means for forcing a second reference current through a second circuit path including the second contact element, the first ESD diode, and the first contact element and measuring a second voltage across the second circuit path, and
means for forcing a third reference current through a third circuit path including the third contact element, the third ESD diode, and the first contact element and measuring a third voltage across the third circuit path;
(d) means for solving three equations representative of the first, second, and third voltages to determine first, second, and third contact resistances between the first contact element and the first terminal, the second contact element and the second terminal, and the third contact element and the third terminal, respectively;
and
(e) means for performing a parametric test operation on the integrated circuit chip to determine a parameter dependent on a voltage of the third terminal by determining a first test current through the third contact resistance and using the first test current to determine a voltage drop across the third contact resistance, and computing a value equal to a measurement voltage of the third contact element offset by the amount of the voltage drop across the third contact resistance to obtain a more accurate measurement value representative of the voltage of the third terminal.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/052,121Filed 7 Feb 2005
Granted: 18 Apr 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G01R 27/205
Measuring earth resistance; Measuring contact resistance, e.g. of earth connections, e.g. plates: measuring contact resistance of connections,…
G01R 31/2886
Testing of integrated circuits [IC]: features relating to contacting the IC under test, e.g. probe heads; chucks
G01R 35/00
Testing or calibrating of apparatus covered by the other groups of this
H10D 89/611
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using diodes as protective elements