FeRAM capacitor stack etch
AssigneeTexas Instruments Incorporated
InventorsFrancis G. Celii, Scott R. Summerfelt, Mahesh Thakre
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Abstract
The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.
Claims5
A method of etching a capacitor stack associated with a ferroelectric memory cell, comprising:
- forming a bottom electrode layer, a PZT ferroelectric layer, a top electrode layer, and a hard mask layer over a substrate;
- patterning the hard mask layer;
- patterning the top electrode layer in accordance with the patterned hard mask;
- patterning the PZT ferroelectric layer, wherein a resulting PZT ferroelectric sidewall edge has a profile having an angle of less than about 88 degrees;
- and
- patterning the bottom electrode layer in accordance with the patterned hard mask, wherein the PZT profile angle of less than about 88 degrees causes a re-deposition rate of bottom electrode material on the PZT sidewall edge during the bottom electrode layer patterning to be less than a removal rate thereof due to ion impingement, thereby preventing bottom electrode material from forming on the PZT ferroelectric layer sidewall during the capacitor stack etch;
- wherein patterning the PZT ferroelectric layer comprises etching using a fluorine gas+Cl2+an oxidizer at a relatively low temperature;
- and
- wherein the temperature of the PZT ferroelectric layer etch is about 60° C.
A method of etching a capacitor stack associated with a ferroelectric memory cell, comprising:
- forming a bottom electrode layer, a PZT ferroelectric layer, a top electrode layer, and a hard mask layer over a substrate;
- patterning the hard mask layer;
- patterning the top electrode layer in accordance with the patterned hard mask;
- patterning the PZT ferroelectric layer, wherein a resulting PZT ferroelectric sidewall edge has a profile having an angle of less than about 88 degrees;
- and
- patterning the bottom electrode layer in accordance with the patterned hard mask, wherein the PZT profile angle of less than about 88 degrees causes a re-deposition rate of bottom electrode material on the PZT sidewall edge during the bottom electrode layer patterning to be less than a removal rate thereof due to ion impingement, thereby preventing bottom electrode material from forming on the PZT ferroelectric layer sidewall during the capacitor stack etch;
- and
- wherein etching the PZT ferroelectric layer comprises using a CHF3+Cl2+O2+N2 at a temperature of about 60° C.
A method of etching a capacitor stack associated with a ferroelectric memory cell, comprising:
- forming a bottom electrode layer, a PZT ferroelectric layer, a top electrode layer, and a hard mask layer over a substrate;
- patterning the hard mask layer;
- patterning the top electrode layer in accordance with the patterned hard mask;
- patterning the PZT ferroelectric layer, wherein a resulting PZT ferroelectric sidewall edge has a profile having an angle of less than about 88 degrees;
- and
- patterning the bottom electrode layer in accordance with the patterned hard mask, wherein the PZT profile angle of less than about 88 degrees causes a re-deposition rate of bottom electrode material on the PZT sidewall edge during the bottom electrode layer patterning to be less than a removal rate thereof due to ion impingement, thereby preventing bottom electrode material from forming on the PZT ferroelectric layer sidewall during the capacitor stack etch;
- wherein patterning the top and bottom electrode layers comprise etching with a Cl2+O2 or a Cl2+CO at substantially high temperature, and
- wherein patterning the PZT ferroelectric layer comprises etching using a fluorine gas+Cl2+an oxidizer at a relatively low temperature.
A method of etching a capacitor stack associated with a ferroelectric memory cell, comprising:
- forming a bottom electrode layer, a PZT ferroelectric layer, a top electrode layer, and a hard mask layer over a substrate;
- patterning the hard mask layer;
- patterning the top electrode layer in accordance with the patterned hard mask;
- patterning the PZT ferroelectric layer, wherein a resulting PZT ferroelectric sidewall edge has a profile having an angle of less than about 88 degrees;
- and
- patterning the bottom electrode layer in accordance with the patterned hard mask, wherein the PZT profile angle of less than about 88 decrees causes a re-deposition rate of bottom electrode material on the PZT sidewall edge during the bottom electrode layer patterning to be less than a removal rate thereof due to ion impingement, thereby preventing bottom electrode material from forming on the PZT ferroelectric layer sidewall during the capacitor stack etch;
- and
- wherein the sidewall edge profile angle of the PZT ferroelectric layer is about 80 degrees or more.
Dependencies are inferred from the claim text.