Memory devices and electronic systems comprising integrated bipolar and FET devices
AssigneeMicron Technology, Inc.
InventorArup Bhattacharyya
Life of this patent
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Abstract
The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.
Claims16
A memory device comprising:
- a crystalline layer separated from a substrate by an insulative material;
- the crystalline layer being less than or equal to about 2000 Å thick and comprising a material which includes silicon and germanium;
- a field effect transistor having a transistor gate and a pair of source/drain regions;
- a bipolar transistor having a collector region, emitter region and base region;
- the collector region and emitter region both being elevationally above the transistor gate;
- the base region electrically connecting with one of the source/drain regions of the field effect transistor;
- and
- wherein the field effect transistor is over the crystalline layer and has an active region extending into the crystalline layer;
- at least a portion of the source/drain regions is comprised by the active region within the crystalline layer;
- the entirety of the active region within the crystalline layer being contained within a single crystal of the material which includes silicon and germanium.
An electronic system, the electronic system comprising a memory device, the memory device including:
- an array of memory cells, at least some of the memory cells including a field effect transistor and a bipolar transistor;
- the field effect transistors having transistor gates and active regions comprising source/drain regions;
- the active regions extending into a crystalline Si/Ge layer;
- the bipolar transistors having collector regions, emitter regions and base regions;
- the collector regions and emitter regions being above the transistor gates;
- the base regions electrically connecting with source/drain regions of the field effect transistors;
- addressing circuitry coupled to the array of memory cells for accessing individual memory cell in the array of memory cells;
- a read circuit coupled to the memory cell array for reading data from memory cells in the array of memory cells;
- and
- wherein the crystalline layer has a relaxed crystalline lattice, and further comprising a strained crystalline lattice layer between the relaxed crystalline lattice and the transistor gates.
Dependencies are inferred from the claim text.