US 7,024,644 B2Granted

IC signal path resistance estimation method

AssigneeCadence Design Systems, Inc.

InventorEddy Pramono

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Abstract

Diffusion effects during an IC fabrication process cause actual dimensions of adjacent conductors in an IC to vary from nominal dimensions specified by data defining the IC layout. A computer-aided design tool processes the layout data to generate a separate database for each layer of the IC, including a separate table corresponding to each grid line of that layer. Each table includes a separate table entry corresponding to each conductor to reside along the table's corresponding grid line, each table entry indicating nominal dimensions and position of its corresponding conductor. The tool sorts grid line tables within each layer's database in an order in which their corresponding grid lines are arranged on that layer, and sorts entries in each table in an order in which their corresponding conductors are to appear along the table's corresponding grid line. The tool then reads each entry in each table of each database only once, in the orders in which the entries and tables are sorted, to obtain information it needs to estimate actual dimensions of each conductor, and estimates the resistance of each conductor as a function of its estimated actual dimensions.

Claims13

Dependent claims

A method for estimating resistances of conductors to reside on layers of an integrated circuit (IC) to be fabricated in accordance with layout data indicating nominal dimensions of each conductor and indicating that conductors on each layer are to be centered at indicated positions along parallel grid lines G=1 through GMAX(L), wherein GMAX(L) for each layer L is an integer greater than 1, and wherein when the IC is fabricated, actual dimensions of each conductor residing on any grid line on any layer are functions of its nominal dimension and of the nominal dimensions and relative position of any adjacent conductor residing on any adjacent grid line of the same layer, the method comprising the steps of:

a. processing the layout data to generate a separate database D(L) for each layer L of the IC, wherein each database D(L) includes a separate table T(L,G) corresponding to each grid line G of layer L, wherein each table T(L,G) of each database D(L) includes a separate table entry corresponding to each conductor to reside along the Gth grid line the Lth layer, wherein each table entry contains information indicating its corresponding conductor's nominal dimensions and its position along the grid line on which it is to reside;
and
b. separately processing the database D(L) for each Lth layer to estimate resistance of each conductor that is to reside along any grid line on the Lth layer as a function of the nominal dimensions and relative positions of that conductor and of any adjacent conductor that is to reside along an adjacent grid line of the same layer,
wherein step b comprises the substeps of, for each value of L:
b1. estimating actual dimensions of conductor sections to reside on a side of grid line G=1 most remote from grid line G=2 of layer L as functions of nominal conductor dimensions and of positions indicated by entries of table T(L,1);
b2. for each value of G from G to GMAX(L)−1, estimating actual dimensions of conductor sections to reside between grid lines G and G+1 of layer L as functions of nominal conductor dimensions and positions indicated by entries of tables T(L,G) and T(L,G+1), and estimating resistance of each conductor along grid line G as a function of estimated actual dimensions of its sections residing on both sides of grid line G;
and
b3. estimating actual dimensions and positions of sections of conductors residing on a side of grid line GMAX(L) most remote from grid line GMAX(L)−1 as functions of nominal conductor dimensions and positions indicated by entries of table T(L,GMAX(L)), and estimating resistance of each conductor to reside along grid line GMAX(L) as a function of estimated actual dimensions of its sections.

5 more elements

Computer-readable media, which when read and executed by a computer causes the computer to carry out a method for estimating resistances of conductors to reside on layers of an integrated circuit (IC) to be fabricated in accordance with IC layout data indicating nominal dimensions of each conductor and indicating that conductors on each layer are to be centered at indicated positions along parallel grid lines G=1 through GMAX(L), wherein GMAX(L) for each layer L is an integer greater than 1, wherein when the IC is fabricated, actual dimensions of each conductor residing on any grid line on any layer are functions of its nominal dimension and of the nominal dimensions and relative position of any adjacent conductor residing on any adjacent grid line of the same layer, wherein the method comprises the steps of:

a. processing the layout data to generate a separate database D(L) for each layer L of the IC, wherein each database D(L) includes a separate table T(L,G) corresponding to each grid line G of layer L, wherein each table T(L,G) of each database D(L) includes a separate table entry corresponding to each conductor to reside along the Gth grid line of the Lth layer, wherein each table entry contains information indicating its corresponding conductor's nominal dimensions and its position along the grid line on which it is to reside;
and
b. separately processing the database D(L) for each Lth layer to estimate resistance of each conductor that is to reside along any grid line on the Lth layer as a function of the nominal dimensions and relative positions of that conductor and of any adjacent conductor that is to reside along an adjacent grid line of the same layer,
wherein step b comprises the substeps of, for each value of L;
b1. estimating actual dimensions of conductor sections to reside on a side of grid line G=1 most remote from grid line G=2 of layer L as functions of nominal conductor dimensions and of positions indicated by entries of table T(L,1);
b2. for each value of G from G to GMAX(L)−1, estimating actual dimensions of conductor sections to reside between grid lines G and G+1 of layers L as functions of nominal conductor dimensions and positions indicated by entries of tables T(L,G) and T(L,G+1), and estimating resistance of each conductor along grid line G as a function of estimated actual dimensions of its sections residing on both sides of grid line G;
and
b3. estimating actual dimensions and positions of sections of conductors residing on a side of grid line GMAX(L) most remote from grid line GMAX(L)−1 as functions of nominal conductor dimensions and positions indicated by entries of table T(L,GMAX(L)), and estimating resistance of each conductor to reside along grid line GMAX(L) as a function of estimated actual dimensions of its sections,
wherein step b1 comprises obtaining information from each table entry of table T(L,1) in an order in which the table entry's corresponding conductors are to reside along grid line G=1;
and
wherein step b2 comprises for each database D(L) obtaining information from each table entry of each table T(L,G) of database D(L) in an order in which the layout data indicates the table's corresponding grid lines are arranged on layer L, with information being obtained from table entries of each table in an order in which the table entry's corresponding conductors are to reside along the grid line corresponding to the table.

8 more elements

A method for estimating resistances of conductors to reside on layers of an integrated circuit (IC) to be fabricated in accordance with layout data indicating nominal dimensions of each conductor and indicating that conductors on each layer are to be centered at indicated positions along parallel grid lines G=1 through GMAX(L) wherein GMAX(L), for each layer L is an integer greater than 1, and wherein when the IC is fabricated, actual dimensions of each conductor residing on any grid line on any layer are functions of its nominal dimension and of the nominal dimensions and relative position of any adjacent conductor residing on any adjacent grid line of the same layer, the method comprising the steps of:

a. processing the layout data to generate a separate database D(L) for each layer L of the IC, wherein each database D(L) includes a seperate table T(L,G) corresponding to each grid line G of layer L, wherein each table T(L,G) of each database D(L) includes a seperate table entry corresponding to each conductor to reside along the Gth grid line the Lth layer, wherein each table entry contains information indicating its corresponding conductor's nominal dimensions and its position along the grid line on which it is to reside;
and
b. separately processing the database D(L) for each Lth layer to estimate resistance of each conductor that is to reside along any grid line on the Lth layer as a function of the nominal dimensions and relative positions of that conductor and of any adjacent conductor that is to reside along an adjacent grid line of the same layer
wherein at step a the entries of the table T(L,G) for each grid line G of each layer L are sorted within the table in accordance with an order in which the layout data indicates their corresponding conductors are arranged along that grid line,
wherein at step a the tables T(L,G) of each database D(L) are sorted within that database in accordance with an order in which the layout data indicates their corresponding grid lines are arranged on layer L,
wherein step b comprises the substeps of, for each value of L:
b1. estimating actual dimensions of conductor sections to reside on a side of grid line G=1 most remote from grid line G=2 of layer L as functions of nominal conductor dimensions and of positions indicated by entries of table T(L,1);
b2. for each value of G from G to GMAX(L)−1, estimating actual dimensions of conductor sections to reside between grid lines G and G+1 of layer L as functions of nominal conductor dimensions and positions indicated by entries of tables T(L,G) and T(L,G+1), and estimating resistances of each conductor along grid line G as a function of estimated actual dimensions of its sections residing on both sides of grid line G;
and
b3. estimating actual dimensions and positions of sections of conductors residing on a side of grid line GMAX(L) most remote from grid line GMAX(L)−1 as functions of nominal conductor dimensions and positions indicated by entries of table T(L,GMAX(L)), and estimating resistances of each conductor to reside along grid line GMAX(L) as a function of estimated actual dimensions of its sections, and
wherein the total resistance R of each conductor is estimated at step b2 in accordance with the expression
R=[Rn2+Rn(ΔR1+ΔR2)+ΔR1ΔR2]/[2Rn+ΔR1+ΔR2]
where L represents a total length of the conductor,
where L1j represents a length of the conductors jth left side box,
where L2j represents a length of the conductors jth right side box,
where ω represents a nominal width of the conductor absent diffraction effects,
where ω1j represents an actual width of the conductors jth left side box,
where ω2j represents an actual width of the conductors jth right side box,
where τ represents a thickness of the conductor,
where ρ represents a resistivity of the conductor,
where A represents a nominal cross-sectional area of the conductor such that A=ωτ,
where Rn represents a nominal resistance of the conductor,
where Rn=2ρL/A,
where ΔRn represents an actual resistance of a jth left side box of a conductor,
where ΔR1j=(ρ/τ)L1j[(1/ω1j)−(2/ω)],
where
Δ
⁢
⁢
R
1
=
∑
j
⁢
⁢
Δ
⁢
⁢
R
1
⁢
j
where
Δ
⁢
⁢
R
2
=
∑
j
⁢
⁢
Δ
⁢
⁢
R
2
⁢
j
.

59 more elements

a. processing the layout data to generate a separate database D(L) for each layer L of the IC, wherein each database D(L) includes a separate table T(L,G) corresponding to each grid line G of layer L, wherein each table T(L,G) of each database D(L) includes a separate table entry corresponding to each conductor to reside along the Gth grid line of the Lth layer, wherein each table entry contains information indicating its corresponding conductor's nominal dimensions and its position along the grid line on which it is to reside;
and
b. seperately processing the database D(L) for each Lth layer to estimate resistance of each conductor that is to reside along any grid line on the Lth layer as a function of the nominal dimensions and relative positions of that conductor and of any adjacent conductor that is to reside along an adjacent grid line of the same layer,
wherein at step a the tables T(L,G) of each database D(L) are sorted within database D(L) in accordance with an order in which the layout data indicates their corresponding grid lines are arranged on layer L,
wherein at step a the entries of the table T(L,G) for each grid line G of each layer L are sorted within the table in accordance with an order in which the layout data indicates their corresponding conductors are arranged along that grid line,
wherein at step a the tables T(L,G) of each database D(L) are sorted within that database in accordance with an order in which the layout data indicates their corresponding grid lines are arranged on layer L,
wherein step b comprises the substeps of, for each value of L:
b1. estimating actual dimensions of conductor sections to reside on a side of grid line G=1 most remote from grid line G2 of layer L as functions of nominal conductor dimensions and of positions indicated by entries of table T(L,1);
b2. for each value of G from G to GMAX(L)−1, estimating actual dimensions of conductor sections to reside between grid lines G and G+1 of layer L as functions of nominal conductor dimensions and positions indicated by entries of tables T(L,G) and T(L,G+1), and estimating resistances of each conductor along grid line G as a function of estimated actual dimensions of its sections residing on both sides of grid line G;
and
b3. estimating actual dimensions and positions of sections of conductors residing on a side of grid line GMAX(L) most remote from grid line GMAX(L)−1 as functions of nominal conductor dimensions and positions indicated by entries of table T(L,GMAX(L)), and estimating resistances of each conductor to reside along grid line GMAX(L) as a function of estimated actual dimensions of its sections, and
wherein the total resistance R of each conductor is estimated at step b2 in accordance with the expression
R=[Rn2+Rn(ΔR1+ΔR2)+ΔR1ΔR2]/[2Rn+ΔR1+ΔR2]
where L represents a total length of the conductor,
where L1j represents a length of the conductor's jth left side box,
where L2j represents a length of the conductor's jth right side box,
where ω represents a nominal width of the conductor absent diffraction effects,
where ω1j represents an actual width of the conductor's jth left side box,
where ω2j represents an actual width of the conductor's jth right side box,
where τ represents a thickness of the conductor,
where ρ represents a resistivity of the conductor,
where A represents a nominal cross-sectional area of the conductor such that A =ωτ,
where Rn represents a nominal resistance of the conductor,
where Rn=2ρL/A,
where ΔR1j represents an actual resistance of a jth left side box of a conductor,
where ΔR1j=(ρ/τ)L1j[(1/ω1j)−(2/ω)],
where
Δ
⁢
⁢
R
1
=
∑
j
⁢
⁢
Δ
⁢
⁢
R
1
⁢
j
where ΔR1j=(ρ/τ)L1j[(1/ω1j)−(2/ω)],
and where
Δ
⁢
⁢
R
2
=
∑
j
⁢
⁢
Δ
⁢
⁢
R
2
⁢
j
.

61 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/435,346Filed 8 May 2003
Published: US 2004/0225975 A111 Nov 2004
Granted: 4 Apr 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G06F 30/367
Circuit design at the analogue level: design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE],…
Y10S 707/99937
Database or file accessing: sorting
Y10S 707/99943
Database schema or data structure: generating database or data structure, e.g. via user interface